Capacitive element, capacitor array, and A/D converter

• US 9,083,371 B2
• Filed: 10/29/2013
• Issued: 07/14/2015
• Est. Priority Date: 12/17/2012
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Aruga, Kenta
• Primary Examiner(s): NGUYEN, LINH V
• Application Number:
  US14/066,291
• Publication Number:
  US 20140167992A1
• Time in Patent Office: 623 Days
• Field of Search: 341/155, 341/172, 341/150
• US Class Current: 1/1
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A capacitive element includes first electrodes and second electrodes that are alternately arranged in a concentric form. Each of the first electrodes and the second electrodes is formed with closed loop form, in at least one wiring layer provided on or above a substrate.

Claims

1. A capacitive element comprising:

a first terminal;

a second terminal;

first electrodes and second electrodes that are alternately arranged in a concentric form in a plurality of wiring layers provided on or above a substrate, each of the first electrodes and the second electrodes being formed with closed loop form, wherein

the first electrodes and the second electrodes are formed in corresponding positions in the plurality of wiring layers,

the first electrodes and the second electrodes are both connected to one of the first terminal and the second terminal in a first wiring layer of the plurality of wiring layers, the first wiring layer being an undermost wiring layer at a substrate side among the plurality of wiring layers, and

the first electrodes and the second electrodes are connected to the first terminal and the second terminal, respectively, in a second wiring layer of the plurality of wiring layers, the second wiring layer being above the first wiring layer, each of the first electrodes and a corresponding one of the second electrodes that is adjacent to the each of the first electrodes being capacitively coupled in the second wiring layer to form a capacitor.

2. The capacitive element according to claim 1, wherein

the first wiring layer is a polysilicon layer formed above the substrate and polysilicon electrodes of transistors formed on the substrate are used as the first electrodes and the second electrodes in the first wiring layer.

3. The capacitive element according to claim 1, the capacitive element comprising:

an impurity region formed in the substrate under the first wiring layer and including a silicidated region to which one of the first terminal and the second terminal is connected.

4. The capacitive element according to claim 1, wherein

a fixed potential is applied at least to an outermost electrode among the first electrodes and the second electrodes alternately arranged in the concentric form.

5. The capacitive element according to claim 1, wherein

the concentric form is a concentric circular form or a concentric polygon form.

6. The capacitive element according to claim 1, wherein

the first electrodes and the second electrodes are formed in a copper wiring process.

7. The capacitive element according to claim 1, wherein

each of the first electrodes and the second electrodes includes no end.

8. A capacitor array including a plurality of unit capacitors arranged in an array form, and defining the number of the unit capacitors used as each of a plurality of capacitive elements in accordance with a relative ratio of capacitance values of the plurality of capacitive elements, the capacitor array comprising:

a first wiring layer which connects the plurality of capacitive elements to a common electrode; and

a second wiring layer which connects the unit capacitors used for each of the plurality of capacitive elements, wherein

each of the plurality of unit capacitors includes;

a first terminal;

a second terminal;

first electrodes and second electrodes that are alternately arranged in a concentric form in a plurality of wiring layers provided on or above a substrate, each of the first electrodes and the second electrodes being formed with closed loop form, wherein

the first electrodes and the second electrodes are formed in corresponding positions in the plurality of wiring layers,

the first electrodes and the second electrodes are both connected to one of the first terminal and the second terminal in a third wiring layer of the plurality of wiring layers, the third wiring layer being an undermost wiring layer at a substrate side among the plurality of wiring layers, and

the first electrodes and the second electrodes are connected to the first terminal and the second terminal, respectively, in a fourth wiring layer of the plurality of wiring layers, the fourth wiring layer being above the third wiring layer, each of the first electrodes and a corresponding one of the second electrodes that is adjacent to the each of the first electrodes being capacitively coupled in the fourth wiring layer to form a capacitor.

9. The capacitor array according to claim 8, wherein

the unit capacitor arranged at an outermost circumference of the capacitor array is a dummy capacitor which is not used as a unit capacitor to be used for the plurality of capacitive elements.

10. The capacitor array according to claim 8, wherein

the unit capacitors arranged in distributed positions in the capacitor array are selected as the unit capacitors used for each of the plurality of capacitive elements.

11. The capacitor array according to claim 8, wherein

the first wiring layer is an undermost wiring layer at a substrate side, and

the second wiring layer is an uppermost wiring layer above a substrate.

12. The capacitor array according to claim 8, wherein

a fixed potential is applied at least to an outermost electrode among the first electrodes and the second electrodes alternately arranged in the concentric form.

13. The capacitor array according to claim 8, wherein

the first electrodes and the second electrodes are formed in a copper wiring process.

14. The capacitor array according to claim 8, wherein

each of the first electrodes and the second electrodes includes no end.

15. An A/D converter comprising:

a capacitor array including a plurality of unit capacitors arranged in an array form, and defining the number of the unit capacitors used as each of a plurality of capacitive elements in accordance with a relative ratio of capacitance values of the plurality of capacitive elements;

a plurality of switches arranged at a periphery of the capacitor array and provided corresponding to the plurality of capacitive elements; and

a comparator arranged at the periphery of the capacitor array and configured to compare input voltage with voltage corresponding to the capacitive elements selected by the plurality of switches, wherein

analog-to-digital conversion of the input voltage is performed, and

the capacitor array includes;

a first wiring layer which connects the plurality of capacitive elements to a common electrode; and

a second wiring layer which connects the unit capacitors used for each of the plurality of capacitive elements, wherein

each of the plurality of unit capacitors includes;

a first terminal;

a second terminal;

first electrodes and second electrodes that are alternately arranged in a concentric form in a plurality of wiring layers provided on or above a substrate, each of the first electrodes and the second electrodes being formed with closed loop form, wherein

the first electrodes and the second electrodes are formed in corresponding positions in the plurality of wiring layers,

the first electrodes and the second electrodes are both connected to one of the first terminal and the second terminal in a third wiring layer of the plurality of wiring layers, the third wiring layer being an undermost wiring layer at a substrate side among the plurality of wiring layers, and

the first electrodes and the second electrodes are connected to the first terminal and the second terminal, respectively, in a fourth wiring layer of the plurality of wiring layers, the fourth wiring layer being above the third wiring layer, each of the first electrodes and a corresponding one of the second electrodes that is adjacent to the each of the first electrodes being capacitively coupled in the fourth wiring layer to form a capacitor.

16. The A/D converter according to claim 15, wherein

a fixed potential is applied at least to an outermost electrode among the first electrodes and the second electrodes alternately arranged in the concentric form.

17. The A/D converter according to claim 15, wherein

the unit capacitor arranged at an outermost circumference of the capacitor array is a dummy capacitor which is not used as a unit capacitor to be used for the plurality of capacitive elements.

18. The A/D converter according to claim 15, wherein

the first wiring layer is an undermost wiring layer at a substrate side, and

the second wiring layer is an uppermost wiring layer above a substrate.

19. An integrated circuit, comprising:

an A/D converter including;

a capacitor array including a plurality of unit capacitors arranged in an array form, and defining the number of the unit capacitors used as each of a plurality of capacitive elements in accordance with a relative ratio of capacitance values of the plurality of capacitive elements;

a plurality of switches arranged at a periphery of the capacitor array and provided corresponding to the plurality of capacitive elements; and

a comparator arranged at the periphery of the capacitor array and configured to compare input voltage with voltage corresponding to the capacitive elements selected by the plurality of switches, wherein

analog-to-digital conversion of the input voltage is performed, and

the capacitor array includes;

a first wiring layer which connects the plurality of capacitive elements to a common electrode; and

a second wiring layer which connects the unit capacitors used for each of the plurality of capacitive elements, wherein

each of the plurality of unit capacitors includes;

a first terminal;

a second terminal;

first electrodes and second electrodes that are alternately arranged in a concentric form in a plurality of wiring layers provided on or above a substrate, each of the first electrodes and the second electrodes being formed with closed loop form, wherein

the first electrodes and the second electrodes are formed in corresponding positions in the plurality of wiring layers,

the first electrodes and the second electrodes are both connected to one of the first terminal and the second terminal in a third wiring layer of the plurality of wiring layers, the third wiring layer being an undermost wiring layer at a substrate side among the plurality of wiring layers, and

the first electrodes and the second electrodes are connected to the first terminal and the second terminal, respectively, in a fourth wiring layer of the plurality of wiring layers, the fourth wiring layer being above the third wiring layer, each of the first electrodes and a corresponding one of the second electrodes that is adjacent to the each of the first electrodes being capacitively coupled in the fourth wiring layer to form a capacitor.