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Method and apparatus for generating jitter test patterns on a high performance serial bus

  • US 9,083,525 B2
  • Filed: 03/25/2013
  • Issued: 07/14/2015
  • Est. Priority Date: 04/21/2000
  • Status: Expired due to Fees
First Claim
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1. An apparatus configured to transmit a jitter test pattern over a communications bus to a device under test, the apparatus comprising:

  • a port configured to at least transmit and receive data over the communications bus;

    a transmission scrambler in data communication with the port; and

    computerized logic in data communication with the port and the transmission scrambler, the logic configured to cause the apparatus to;

    generate one or more jitter test patterns comprising at least one asynchronous packet;

    transmit the one or more jitter test patterns to the device under test;

    disable the transmission scrambler after synchronization with the device under test has been achieved; and

    retransmit the one or more jitter test patterns at least once to the device under test.

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