Method and apparatus for generating jitter test patterns on a high performance serial bus
First Claim
1. An apparatus configured to transmit a jitter test pattern over a communications bus to a device under test, the apparatus comprising:
- a port configured to at least transmit and receive data over the communications bus;
a transmission scrambler in data communication with the port; and
computerized logic in data communication with the port and the transmission scrambler, the logic configured to cause the apparatus to;
generate one or more jitter test patterns comprising at least one asynchronous packet;
transmit the one or more jitter test patterns to the device under test;
disable the transmission scrambler after synchronization with the device under test has been achieved; and
retransmit the one or more jitter test patterns at least once to the device under test.
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Accused Products
Abstract
The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.
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Citations
19 Claims
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1. An apparatus configured to transmit a jitter test pattern over a communications bus to a device under test, the apparatus comprising:
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a port configured to at least transmit and receive data over the communications bus; a transmission scrambler in data communication with the port; and computerized logic in data communication with the port and the transmission scrambler, the logic configured to cause the apparatus to; generate one or more jitter test patterns comprising at least one asynchronous packet; transmit the one or more jitter test patterns to the device under test; disable the transmission scrambler after synchronization with the device under test has been achieved; and retransmit the one or more jitter test patterns at least once to the device under test. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of performing a jitter test over a high performance serial bus, the method comprising:
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generating a test pattern, the test pattern comprising one or more asynchronous packets; transmitting the one or more asynchronous packets to at least one port of a device under test; disabling a transmit scrambler after synchronizing with the device under test; and repeating the act of transmitting for at least a portion of the one or more asynchronous packets one or more times. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A computer readable apparatus comprising a non-transitory storage medium configured to have at least one computer program stored thereon, the at least one program comprising a plurality of instructions to test for jitter, the plurality of instructions configured to, when executed, cause an apparatus to:
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generate a jitter test pattern comprising at least an asynchronous packet; transmit at least a portion of the jitter test pattern to a device under test; disable a transmit scrambler of the apparatus after synchronization with the device under test has been achieved; and retransmit the at least portion of the jitter test pattern at least once more to the device under test; wherein the transmit scrambler is configured to scramble the transmission of the at least portion of the jitter test pattern. - View Dependent Claims (16, 17, 18, 19)
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Specification