Method and apparatus for generating jitter test patterns on a high performance serial bus

• US 9,083,525 B2
• Filed: 03/25/2013
• Issued: 07/14/2015
• Est. Priority Date: 04/21/2000
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Whitby-Strevens, Colin
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US13/850,159
• Publication Number:
  US 20130287083A1
• Time in Patent Office: 841 Days
• US Class Current: 1/1
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04L 1/244 test sequence generators

Abstract

The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Claims

1. An apparatus configured to transmit a jitter test pattern over a communications bus to a device under test, the apparatus comprising:

a port configured to at least transmit and receive data over the communications bus;

a transmission scrambler in data communication with the port; and

computerized logic in data communication with the port and the transmission scrambler, the logic configured to cause the apparatus to;

generate one or more jitter test patterns comprising at least one asynchronous packet;

transmit the one or more jitter test patterns to the device under test;

disable the transmission scrambler after synchronization with the device under test has been achieved; and

retransmit the one or more jitter test patterns at least once to the device under test.

2. The apparatus of claim 1, wherein:

the logic is further configured to cause the apparatus to scramble at least one of the one or more jitter test patterns via the transmission scrambler; and

the transmitted one or more jitter test patterns comprise at least the scrambled at least one jitter test pattern.

3. The apparatus of claim 1, wherein the port is configured to operate at a maximum operating speed of a port of the device under test.

4. The apparatus of claim 1, wherein the communications bus comprises an IEEE Std. 1394b compliant serial bus.

5. The apparatus of claim 1, wherein the generated one or more jitter test patterns comprise at least an asynchronous packet having a length equal to a maximum allowed value for the communications bus.

6. The apparatus of claim 1, wherein the logic is further configured to cause the apparatus to:

read a data value stored at the port of the device under test; and

determine a jitter error rate for the port of the device under test, the determination based at least in part on the read data value.

7. A method of performing a jitter test over a high performance serial bus, the method comprising:

generating a test pattern, the test pattern comprising one or more asynchronous packets;

transmitting the one or more asynchronous packets to at least one port of a device under test;

disabling a transmit scrambler after synchronizing with the device under test; and

repeating the act of transmitting for at least a portion of the one or more asynchronous packets one or more times.

8. The method of claim 7, further comprising determining an error rate due to jitter of the at least one port by at least reading a port register associated with the at least one port.

9. The method of claim 7, wherein the generated test pattern comprises at least a low density pattern portion and a high density pattern portion.

10. The method of claim 9, wherein:

the low density pattern portion comprises at least 167 10-bit characters; and

the high density portion comprises at least 50 10-bit characters.

11. The method of claim 7, wherein the generated test pattern comprises a repeated sequence of maximum size asynchronous packets.

12. The method of claim 7, further comprising scrambling the one or more asynchronous packets prior to the transmitting.

13. The method of claim 7, wherein the high performance serial bus comprises an IEEE 1394b compliant serial bus.

14. The method of claim 7, wherein the one or more asynchronous packets consist of an alternating byte pattern.

15. A computer readable apparatus comprising a non-transitory storage medium configured to have at least one computer program stored thereon, the at least one program comprising a plurality of instructions to test for jitter, the plurality of instructions configured to, when executed, cause an apparatus to:

generate a jitter test pattern comprising at least an asynchronous packet;

transmit at least a portion of the jitter test pattern to a device under test;

disable a transmit scrambler of the apparatus after synchronization with the device under test has been achieved; and

retransmit the at least portion of the jitter test pattern at least once more to the device under test;

wherein the transmit scrambler is configured to scramble the transmission of the at least portion of the jitter test pattern.

16. The computer readable apparatus of claim 15, wherein the generated jitter test pattern comprises a random pattern comprising a repeated sequence of maximum size asynchronous packets.

17. The computer readable apparatus of claim 15, wherein the plurality of instructions are further configured to, when executed, cause the apparatus to:

read a port register of the device under test which received the transmitted at least portion of the jitter test pattern; and

calculate an error rate associated with jitter based at least in part on data read from the port register.

18. The computer readable apparatus of claim 15, wherein the plurality of instructions are further configured to, when executed, cause the apparatus to

enable the transmit scrambler of the apparatus.

19. The computer readable apparatus of claim 18, wherein the at least asynchronous packet comprises a packet comprising an alternating byte pattern.