Devices having different effective series resistance states and methods for controlling such devices

• US 9,083,575 B2
• Filed: 03/25/2011
• Issued: 07/14/2015
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hollis, Timothy
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Ortiz, Elim
• Application Number:
  US13/072,402
• Publication Number:
  US 20120242157A1
• Time in Patent Office: 1,572 Days
• Field of Search: 307/149, 307/99
• US Class Current: 1/1
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

Devices and methods are described, such as those including parallel paths coupled between a first power supply and a second power supply. The parallel paths include different values of capacitance to reduce unwanted variations as a function of current demand frequency such as resonance. A selectable resistance is provided along one or more parallel paths, and can be varied during different times in a signal burst.

Claims

1. A device, comprising:

a first pathway comprising a first effective series resistance and a first capacitance, coupled between a first power supply and a second power supply;

a second pathway comprising a second effective series resistance and a second capacitance, the second pathway coupled in parallel to the first pathway between the first power supply and the second power supply, wherein the second effective series resistance is switchable between a higher resistance state and a lower resistance state;

a circuit to switch the second effective series resistance to the lower resistance state during a portion of a signal, and to switch the second effective series resistance to the higher resistance state during another portion of the signal, wherein the circuit is configured to switch the second effective series resistance to the lower resistance state before a first digit in a burst of the signal, and is configured to switch the second effective series resistance to the higher resistance state after the first digit of the signal.

2. The device of claim 1, wherein the pathways are located on a semiconductor die.

3. The device of claim 1, wherein the portion is an initial portion and the other portion is a remaining portion.

4. The device of claim 1, wherein the portion is at the beginning of a burst of the signal.

5. The device of claim 1, wherein the circuit includes a passgate to switch the second effective series resistance to the lower resistance state and to switch the second effective series resistance to the higher resistance state.

6. The device of claim 5, wherein the passgate comprises an NMOS passgate.

7. The device of claim 4, wherein the signal is a data signal.

8. A device, comprising:

a first pathway comprising a first effective series resistance and a first capacitance, coupled between a first power supply and a second power supply;

a second pathway having a second effective series resistance higher than the first effective series resistance and a second capacitance higher than the first capacitance, the second pathway coupled in parallel with the first pathway between the first power supply and the second power supply;

a third pathway comprising a third effective series resistance higher than the first effective series resistance and lower than the second effective series resistance and a third capacitance higher than the first capacitance, the third pathway coupled in parallel with the first pathway between the first power supply and the second power supply;

a circuit to activate the third pathway during a portion of a signal, and to activate the second pathway during another portion of the signal, wherein the circuit is configured to switch the second effective series resistance to a lower resistance state at a beginning of a burst of the signal, and is configured to switch the second effective series resistance to a higher resistance state after the beginning of the burst of the signal.

9. The device of claim 8, wherein second capacitance and third capacitance are approximately the same.

10. The device of claim 9, wherein the second capacitance is approximately 4 times the first capacitance.

11. The device of claim 9, wherein the first pathway is located on a semiconductor die.