Polar receiver with adjustable delay and signal processing metho

• US 9,083,588 B1
• Filed: 04/23/2014
• Issued: 07/14/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Innophase, Inc.
• Original Assignee: Innophase, Inc.
• Inventors: Xu, Yang, Munoz Hermoso, Sara
• Primary Examiner(s): Tran, Khanh C
• Application Number:
  US14/260,021
• Time in Patent Office: 447 Days
• Field of Search: 375324-325, 375/346, 375/348, 375/350, 375/371, 375/373, 375/376
• US Class Current: 1/1
• CPC Class Codes: H03B 2200/007 Generation of oscillations based on harmonic frequencies, e.g. overtone oscillators
• CPC Class Codes: H03B 2200/0074 Locking of an oscillator by injecting an input signal directly into the oscillator
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03D 5/00 Circuits for demodulating amplitude-modulated or angle-modulated oscillations at will H03D9/00, H03D11/00 take precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H04L 27/227 using coherent demodulation
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

Adjusting a relative phase within a polar receiver to reduce a DC error, the polar receiver having (i) a harmonic ILO having an RF modulated signal input and a phase-compressed divided-frequency output, (ii) a fundamental ILO connected to the phase-compressed divided-frequency output and having a phase-locking output, (iii) a delay element, and (iv) a phase discriminator connected to the delay element output and to the phase-locking output, and having a phase-detection output representative of a phase difference between signals on the delay output and the phase-locking output.

Claims

1. An apparatus comprising:

a harmonic injection-locked oscillator (ILO) having an RF modulated signal input and a phase-compressed divided-frequency output;

a fundamental ILO connected to the phase-compressed divided-frequency output and a phase-locking output;

an adjustable delay circuit connected to the phase-compressed divided-frequency output and a having a delay output;

a phase discriminator connected to the delay output and to the phase-locking output, and having a phase-detection output representative of a phase difference between signals on the delay output and the phase-locking output.

2. The apparatus of claim 1 wherein the adjustable delay circuit comprises serially-connected inverter circuits.

3. The apparatus of claim 2 wherein the serially-connected inverter circuits comprises a first inverter circuit having a variable current output.

4. The apparatus of claim 3 wherein the variable output current is controlled by adjusting a bias current in the first inverter circuit.

5. The apparatus of claim 3 wherein the variable current output is used to charge and discharge a gate-source capacitance of a second inverter circuit of the serially-connected inverter circuits.

6. The apparatus of claim 2 wherein the serially-connected inverter circuits comprises a variable capacitance interposed between a first inverter circuit and a second inverter circuit.

7. The apparatus of claim 6 wherein the variable capacitance comprises a switched capacitor bank.

8. The apparatus of claim 1 further comprising a control circuit configured to adjust the adjustable delay circuit in response to a measurement of the phase-detection output.

9. The apparatus of claim 1 wherein the phase discriminator is a mixer and low-pass filter.

10. A method comprising:

adjusting a resonance frequency of a fundamental injection-locked oscillator (ILO) to change the free-running frequency of the fundamental ILO;

injecting a non-phase modulated signal into a second-harmonic ILO and connecting an output of the second-harmonic ILO to the fundamental ILO; and

adjusting a relative delay between the output of the second-harmonic ILO and an output of the fundamental ILO using a delay circuit.

11. The method of claim 10 further comprising adjusting one or more parameters of the second-harmonic ILO wherein the one or more parameters include a parameter selected from the group consisting of an injection coefficient, a quality factor, and a resonance frequency of the ILO.

12. The method of claim 10 further comprising obtaining a phase measurement of a phase relationship between the output of the second-harmonic ILO and the output of the fundamental ILO, and wherein the relative delay is adjusted in response to the phase measurement.

13. The method of claim 12 wherein the phase measurement is obtained from a phase discriminator.

14. The method of claim 10 wherein the relative delay is adjusted by altering a bias current of an inverter within the delay circuit.

15. The method of claim 10 wherein the relative delay is adjusted by altering a variable capacitance of a serially-connected inverter circuit within the delay circuit.

16. The method of claim 10 further comprising re-adjusting at least one parameter of the fundamental ILO after adjusting the relative delay with the delay circuit.

17. The method of claim 10 further comprising adjusting a resonance frequency of the second harmonic ILO to change the free-running frequency of the second harmonic ILO.

18. An apparatus comprising:

a harmonic injection-locked oscillator (ILO) operative to receive an RF modulated signal input and to provide a phase-compressed divided-frequency signal output;

a fundamental ILO operative to receive the phase-compressed divided-frequency signal output and to provide a phase-locking signal output;

an adjustable delay circuit configured to adjust a relative phase difference between the phase-compressed divided-frequency signal and the phase-locking signal;

a phase discriminator operative to receive the phase-compressed divided-frequency signal and the phase-locking signal and to provide a phase-detection output representative of a phase difference between the phase-compressed divided-frequency signal and the phase-locking signal.

19. The apparatus of claim 18, wherein the adjustable delay circuit is connected between the harmonic ILO and the phase discriminator and is operative to retard the phase of the phase-compressed divided-frequency signal.

20. The apparatus of claim 18, wherein the adjustable delay circuit is connected between the harmonic ILO and fundamental ILO and is operative to retard the phase of the phase-locking signal.