Solid state nanopore devices for nanopore applications to improve the nanopore sensitivity and methods of manufacture

• US 9,085,120 B2
• Filed: 08/26/2013
• Issued: 07/21/2015
• Est. Priority Date: 08/26/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Astier, Yann, Bai, Jingwei, Smith, Joshua T., Papa Rao, Satyavolu, Reuter, Kathleen
• Primary Examiner(s): NGUYEN, DUY T V
• Application Number:
  US14/010,158
• Publication Number:
  US 20150056732A1
• Time in Patent Office: 694 Days
• Field of Search: 438/49
• US Class Current: 1/1
• CPC Class Codes: B32B 2250/03 3 layers
• CPC Class Codes: B32B 2307/204 Di-electric
• CPC Class Codes: B32B 2457/00 Electrical equipment
• CPC Class Codes: B32B 3/266 characterised by an apertured layer, the apertures going through the whole thickness of the layer, e.g. expanded metal, perforated layer, slit layer regular cells B32B3/12
• CPC Class Codes: B81B 1/004 Through-holes, i.e. extending from one face to the other face of the wafer
• CPC Class Codes: B81B 2201/0214 Biosensors; Chemical sensors
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0353 Holes
• CPC Class Codes: B81C 1/00087 Holes
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4146 involving nanosized elements, e.g. nanotubes, nanowires
• CPC Class Codes: G01N 33/48721 Investigating individual macromolecules, e.g. by translocation through nanopores Coulter counters in general G01N15/12; fabrication methods for nanoscale apertures B81B1/00; sequencing of nucleic acids C12Q1/68
• CPC Class Codes: Y10T 428/24322 Composite web or sheet

Abstract

Solid state nanopore devices for nanopore applications and methods of manufacture are disclosed herein. The method includes forming a membrane layer on an underlying substrate. The method further includes forming a hole in the membrane layer. The method further comprises plugging the hole with a sacrificial material. The method further includes forming a membrane over the sacrificial material. The method further includes removing the sacrificial material within the hole and portions of the underlying substrate. The method further includes drilling an opening in the membrane, aligned with the hole.

Claims

1. A method, comprising:

forming a membrane layer on an underlying semiconductor substrate;

forming a hole in the membrane layer;

plugging the hole with a sacrificial material;

forming a membrane over a top surface of the sacrificial material;

forming an optional sacrificial material over the sacrificial material and under the membrane;

removing the sacrificial material within the hole and portions of the underlying semiconductor substrate; and

drilling an opening in the membrane, aligned with the hole, after the sacrificial material has been removed,

wherein the membrane remains directly over remaining portions of the optional sacrificial material during the removing step.

2. The method of claim 1, wherein the membrane layer and the membrane are both SiNx.

3. The method of claim 2, wherein the membrane layer is formed to a thickness of about 20 nm to 500 nm using low-pressure chemical vapor deposition (LPCVD) processes and the membrane has a thickness of about 10 nm.

4. The method of claim 1, wherein the opening is about 5 nm in diameter, suspended over the hole in the membrane layer.

5. The method of claim 1, wherein the opening is an array of openings.

6. The method of claim 1, wherein the sacrificial material is blanketed deposited to a thickness greater than a depth of the hole and is thereafter planarized to form a sacrificial plug.

7. The method of claim 6, wherein the membrane is formed over the sacrificial plug.

8. The method of claim 6, further comprising removing the sacrificial plug and portions of the underlying semiconductor substrate to form the hole.

9. The method of claim 8, wherein the opening is formed by one of a transmission electron microscopy (TEM) process and focused ion beam (FIB) process, after the removing of the sacrificial plug.

10. The method of claim 1, wherein the optional sacrificial material is a same material as used for the sacrificial plug.

12. The method of claim 1, further comprising forming electrodes on sides of the hole.

11. A method, comprising:

forming a membrane layer on an underlying semiconductor substrate;

forming a hole in the membrane layer;

plugging the hole with a sacrificial material, wherein the sacrificial material is blanketed deposited to a thickness greater than a depth of the hole and is thereafter planarized to form a sacrificial plug;

forming a membrane over the sacrificial plug;

forming an optional sacrificial material over the sacrificial plug and under the membrane;

removing the sacrificial plug within the hole and portions of the underlying semiconductor substrate; and

drilling an opening in the membrane, aligned with the hole, after the sacrificial plug is removed,

wherein the forming of the hole also removes a portion of the optional sacrificial material to form an air gap between the membrane layer and the membrane, and

wherein the membrane remains directly over remaining portions of the optional sacrificial material during the removing step.

13. A method, comprising:

forming a dielectric layer on an underlying semiconductor substrate;

forming a hole in the dielectric layer by lithography and etching processes;

plugging the hole with a sacrificial material to form a sacrificial plug, the plugging comprising;

blanket depositing of an oxide material to a thickness greater than the depth of the hole; and

planarizing the oxide material to a surface of the dielectric layer;

forming a membrane over a top surface of the sacrificial plug;

forming an optional sacrificial material over the sacrificial plug and under the membrane;

removing the sacrificial plug and portions of the underlying semiconductor substrate; and

drilling an opening in the membrane, aligned with the hole, after the sacrificial plug has been removed,

wherein the membrane remains directly over remaining portions of the optional sacrificial material during the removing step.

14. The method of claim 13, wherein:

the dielectric layer and the membrane are both SiNx;

the dielectric layer is formed to a thickness of about 20 nm to 500 nm using chemical vapor deposition (LPCVD) processes;

the membrane has a thickness of about 10 nm; and

the opening is about 5 nm in diameter, suspended over the hole in the dielectric layer.

15. The method of claim 13, wherein the opening is formed by one of a transmission electron microscopy (TEM) process and focused ion beam (FIB) process, after the removing of the sacrificial plug.

17. The method of claim 13, further comprising forming electrodes on sides of the hole.

16. A method, comprising:

forming a dielectric layer on an underlying semiconductor substrate;

forming a hole in the dielectric layer by lithography and etching processes;

plugging the hole with a sacrificial material to form a sacrificial plug, the plugging comprising;

blanket depositing of an oxide material to a thickness greater than the depth of the hole; and

planarizing the oxide material to a surface of the dielectric layer;

forming a membrane over a top surface of the sacrificial plug;

forming an optional sacrificial material over the sacrificial plug and under the membrane, wherein;

the optional sacrificial material is a same material as used for the sacrificial plug; and

the forming of the hole removes a portion of the optional sacrificial material to form an air gap between the dielectric layer and the membrane;

removing the sacrificial plug and portions of the underlying semiconductor substrate; and

drilling an opening in the membrane, aligned with the hole, after the sacrificial plug is removed,

wherein the opening is formed by one of a transmission electron microscopy (TEM) process and focused ion beam (FIB) process, after the removing of the sacrificial plug, and

wherein the membrane remains directly over remaining portions of the optional sacrificial material during the removing step.