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Timing-aware test generation and fault simulation

  • US 9,086,454 B2
  • Filed: 10/14/2013
  • Issued: 07/21/2015
  • Est. Priority Date: 04/27/2006
  • Status: Active Grant
First Claim
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1. A method of generating test patterns for testing an integrated circuit, comprising:

  • identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;

    determining that the identified fault is to be removed from a fault list, the determination being based at least in part on a relative difference between actual slack and static slack of the shortest sensitized path detecting the identified fault, wherein the actual slack is determined by actual path delay through the shortest sensitized path detecting the fault and the static slack is determined by static path delay through the shortest sensitized path detecting the fault;

    modifying the fault list by removing the identified fault; and

    storing the modified fault list.

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