Centralized management of high-contention cache lines in multi-processor computing environments

• US 9,086,974 B2
• Filed: 09/26/2013
• Issued: 07/21/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Cain, Harold W. III, Gschwind, Michael K., Michael, Maged M., Salapura, Valentina, Schwarz, Eric M., Shum, Chung-Lung K.
• Primary Examiner(s): Sun, Michael
• Application Number:
  US14/037,958
• Publication Number:
  US 20150089155A1
• Time in Patent Office: 663 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Communications detected on a coherence interconnect may indicate that a cache line is associated with performance-reducing events. A high-contention cache line may be placed in sub-line coherency mode. Caches accessing the cache line are notified that the cache line is in sub-line coherency mode. The cache line may be associated with a counter in a centralized detection table that is incremented based on detecting the communications. The cache line may be a high-contention cache line when the counter satisfies a high-contention criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.

Claims

1. A method for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the method comprising:

monitoring, with a centralized detector, communications on the coherence interconnect;

detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

based on the detecting, determining that the first cache line is a high-contention cache line;

based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and

notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode.

2. The method of claim 1, wherein the first communication is a signal on the coherence interconnect, the signal raised in response to detecting a conflicting access of the first cache line while executing a transaction in the computing environment, wherein the performance-reducing event is a transactional abort.

3. The method of claim 1, wherein the first communication is a message on the coherence interconnect, the message sent in response to detecting an access of the first cache line, the first cache line previously invalidated by a coherence event, and wherein the performance-reducing event is a coherence request.

4. The method of claim 1, wherein the notifying comprises:

observing a request for the first cache line on the coherence interconnect; and

raising a signal on the coherence interconnect in response to the observing, the signal indicating that the first cache line is in the sub-line coherency mode.

5. The method of claim 1, wherein the notifying comprises:

observing a request for the first cache line on the coherence interconnect; and

modifying the request for the first cache line to indicate that the first cache line is in the sub-line coherency mode.

6. The method of claim 1, wherein the determining that the first cache line is the high-contention cache line comprises:

incrementing a counter in an entry in a detection table, the entry associating the counter with the first cache line; and

determining that the incremented counter satisfies a high-contention criterion.

7. A computer system for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising;

monitoring, with a centralized detector, communications on the coherence interconnect;

detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

based on the detecting, determining that the first cache line is a high-contention cache line;

based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and

notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode.

8. The computer system of claim 7, wherein the determining that the first cache line is the high-contention cache line comprises:

incrementing a counter in an entry in a detection table, the entry associating the counter with the first cache line; and

determining that the incremented counter satisfies a high-contention criterion.

9. The computer system of claim 8, wherein the determining that the incremented counter satisfies the high-contention criterion comprises:

determining that the incremented counter has reached a threshold value.

10. The computer system of claim 8, wherein the determining that the incremented counter satisfies the high-contention criterion comprises:

calculating a percentage, the percentage based on the incremented counter and a total number of accesses of cache lines resulting in performance-reducing events in the computing environment; and

determining that the percentage has reached a threshold value.

11. The computer system of claim 8, wherein the method further comprises:

determining that a reset criterion associated with the counter is satisfied;

resetting the counter based on the determining that the reset criterion is satisfied; and

placing the first cache line in the full-line coherency mode based on the determining that the reset criterion is satisfied.

12. The computer system of claim 11, wherein the reset criterion is selected from the group consisting of:

a period of time elapses;

a number of transactions complete;

a number of instructions complete; and

a cache line associated with the counter is cast out of the cache.

13. The computer system of claim 8, wherein the entry further associates the counter with at least one cache line adjacent to the first cache line.

14. The computer system of claim 8, wherein the entry further associates the counter with a hash value of a memory address associated with the first cache line.

15. A computer program product for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising;

monitoring, with a centralized detector, communications on the coherence interconnect;

detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

based on the detecting, determining that the first cache line is a high-contention cache line;

based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and

notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode.

16. The computer program product of claim 15, wherein the first communication is a signal on the coherence interconnect, the signal raised in response to detecting a conflicting access of the first cache line while executing a transaction in the computing environment, wherein the performance-reducing event is a transactional abort.

17. The computer program product of claim 15, wherein the first communication is a message on the coherence interconnect, the message sent in response to detecting an access of the first cache line, the first cache line previously invalidated by a coherence event, and wherein the performance-reducing event is a coherence request.

18. The computer program product of claim 15, wherein the determining that the first cache line is the high-contention cache line comprises:

incrementing a counter in an entry in a detection table, the entry associating the counter with the first cache line; and

determining that the incremented counter satisfies a high-contention criterion.

19. The computer program product of claim 18, wherein the entry further associates the counter with at least one cache line adjacent to the first cache line.

20. The computer program product of claim 18, wherein the entry further associates the counter with a hash value of a memory address associated with the first cache line.