Centralized management of high-contention cache lines in multi-processor computing environments
First Claim
1. A method for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the method comprising:
- monitoring, with a centralized detector, communications on the coherence interconnect;
detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;
based on the detecting, determining that the first cache line is a high-contention cache line;
based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and
notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode.
8 Assignments
0 Petitions
Accused Products
Abstract
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Communications detected on a coherence interconnect may indicate that a cache line is associated with performance-reducing events. A high-contention cache line may be placed in sub-line coherency mode. Caches accessing the cache line are notified that the cache line is in sub-line coherency mode. The cache line may be associated with a counter in a centralized detection table that is incremented based on detecting the communications. The cache line may be a high-contention cache line when the counter satisfies a high-contention criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.
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Citations
20 Claims
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1. A method for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the method comprising:
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monitoring, with a centralized detector, communications on the coherence interconnect; detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; based on the detecting, determining that the first cache line is a high-contention cache line; based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer system for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the computer system comprising:
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a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising; monitoring, with a centralized detector, communications on the coherence interconnect; detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; based on the detecting, determining that the first cache line is a high-contention cache line; based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A computer program product for cache management in a multi-processor computing environment, the computing environment including a plurality of caches configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the plurality of caches associated with a coherence interconnect, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising; monitoring, with a centralized detector, communications on the coherence interconnect; detecting a first communication associated with a first cache line in the monitored communications, the first communication indicating an access of the first cache line resulting in a first performance-reducing event, the first cache line in a full-line coherency mode, wherein cache control logic associated with the first cache line is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; based on the detecting, determining that the first cache line is a high-contention cache line; based on the determining, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and notifying caches accessing the first cache line that the first cache line is in the sub-line coherency mode. - View Dependent Claims (16, 17, 18, 19, 20)
Specification