Wireless processor, wireless memory, information system, and semiconductor device

• US 9,087,280 B2
• Filed: 05/01/2014
• Issued: 07/21/2015
• Est. Priority Date: 07/14/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kato, Kiyoshi, Koyama, Jun, Shionoiri, Yutaka
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US14/266,930
• Publication Number:
  US 20140231882A1
• Time in Patent Office: 446 Days
• Field of Search: 257/414, 257/252, 257/E21.662, 257/E31.041, 257/E27.1, 257/E29.117
• US Class Current: 1/1
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

Claims

1. A wireless processor comprising:

a first antenna; and

an element formation region comprising a first transistor and a second transistor,

wherein the first transistor comprises;

a first semiconductor layer over a substrate;

a first gate insulating layer over the first semiconductor layer; and

a first gate over the first gate insulating layer,

wherein the second transistor comprises;

a second gate over the substrate;

a second gate insulating layer over the second gate; and

a second semiconductor layer over the second gate insulating layer,

wherein the wireless processor is attached without a wire connection on an outside of a body of a semiconductor device, the semiconductor device comprising a second antenna, and

wherein the wireless processor and the semiconductor device transmit and receive data with each other by using the first antenna and the second antenna wirelessly.

2. The wireless processor according to claim 1, further comprising a power circuit and a CPU,

wherein the power circuit is configured to generate power by receiving electromagnetic waves through the first antenna and the second antenna, and supply the generated power to the CPU.

3. The wireless processor according to claim 1, further comprising a power circuit and a memory,

wherein the power circuit is configured to generate power by receiving electromagnetic waves through the first antenna and the second antenna, and supply the generated power to the memory.

4. The wireless processor according to claim 1, wherein the element formation region is fixed over a flexible substrate.

5. The wireless processor according to claim 1, wherein the wireless processor is attached on the outside of the body of the semiconductor device by an attaching agent.

6. A wireless memory comprising:

a first antenna; and

an element formation region comprising a first transistor and a second transistor,

wherein the first transistor comprises;

a first semiconductor layer over a substrate;

a first gate insulating layer over the first semiconductor layer; and

a first gate over the first gate insulating layer,

wherein the second transistor comprises;

a second gate over the substrate;

a second gate insulating layer over the second gate; and

a second semiconductor layer over the second gate insulating layer,

wherein the wireless memory is attached without a wire connection on an outside of a body of a semiconductor device, the semiconductor device comprising a second antenna, and

wherein the wireless memory and the semiconductor device transmit and receive data with each other by using the first antenna and the second antenna wirelessly.

7. The wireless memory according to claim 6, further comprising a power circuit, a nonvolatile memory, and a volatile memory,

wherein the power circuit is configured to generate power by receiving electromagnetic waves through the first antenna and the second antenna, and supply the generated power to the nonvolatile memory and the volatile memory.

8. The wireless memory according to claim 6, further comprising a power circuit and a memory interface,

wherein the power circuit is configured to generate power by receiving electromagnetic waves through the first antenna and the second antenna, and supply the generated power to the memory interface.

9. The wireless memory according to claim 6, wherein the element formation region is fixed over a flexible substrate.

10. The wireless memory according to claim 6, wherein the wireless memory is attached on the outside of the body of the semiconductor device by an attaching agent.