Determining design coordinates for wafer defects

• US 9,087,367 B2
• Filed: 08/31/2012
• Issued: 07/21/2015
• Est. Priority Date: 09/13/2011
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Chang, Ellis, Van Riet, Michael J., Park, Allen, Zafar, Khurram, Bhattacharyya, Santosh
• Primary Examiner(s): Koziol, Stephen R
• Assistant Examiner(s): Gilliard, Delomia
• Application Number:
  US13/601,891
• Publication Number:
  US 20130064442A1
• Time in Patent Office: 1,054 Days
• Field of Search: 382/149
• US Class Current: 1/1
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: G06T 7/74 involving reference images or patches

Abstract

Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

Claims

1. A computer-implemented method for determining design coordinates for defects detected on a wafer, comprising:

aligning a design for a wafer to images generated by a defect review tool at locations of defects on the wafer, wherein the defects are detected in multiple swaths scanned on the wafer by a wafer inspection tool prior to said aligning and prior to generation of the images by the defect review tool, wherein the locations of the defects at which the defect review tool generates the images are determined by the wafer inspection tool, wherein the defects comprises two or more first defects detected in a first of the multiple swaths and two or more second defects detected in a second of the multiple swaths, and wherein said aligning comprises overlaying portions of the design with the images generated by the defect review tool at the locations of the defects on the wafer;

determining a position of each of the defects in design coordinates based on results of said aligning;

separately determining at least a first defect position offset for the first of the multiple swaths, based on the design coordinates for each of the first defects and a position for each of the first defects determined by the wafer inspection tool, and a second defect position offset for the second of the multiple swaths, based on the design coordinates for each of the second defects and a position for each of the second defects determined by wafer inspection tool; and

determining design coordinates for other defects detected in the multiple swaths by the wafer inspection tool by applying the first defect position offset to positions of the other defects determined by the wafer inspection tool that were detected in the first of the multiple swaths and applying the second defect position offset to positions of the other defects determined by the wafer inspection tool that were detected in the second of the multiple swaths, wherein said aligning, determining the position, separately determining at least the first and second defect position offsets, and determining the design coordinates are performed by a computer system.

2. The method of claim 1, wherein the defects and the other defects comprise all defects detected on the wafer.

3. The method of claim 1, wherein said aligning, determining the position, separately determining at least the first and second defect position offsets, and determining the design coordinates produce design coordinates for the other defects that are accurate to within one pixel size of a pixel used by the wafer inspection tool when inspecting the wafer.

4. The method of claim 1, wherein said aligning, determining the position, separately determining at least the first and second defect position offsets, and determining the design coordinates produce design coordinates for the other defects that have an accuracy approximately equal to an accuracy of the defect review tool for determining a location of the defects within the images.

5. The method of claim 1, wherein the design is provided in a Graphical Data System (GDS) or Open Artwork System Interchange Standard (OASIS) file.

6. The method of claim 1, further comprising acquiring the design from an electronic design automation (EDA) tool.

7. The method of claim 1, wherein the defect review tool is a scanning electron microscope.

8. The method of claim 1, wherein the wafer inspection tool is an optical inspection tool.

9. The method of claim 1, wherein the wafer inspection tool is an electron beam-based inspection tool.

10. The method of claim 1, further comprising sampling the defects for which the images are generated by the defect review tool based on the swath in which the defects are detected.

11. The method of claim 1, further comprising locating the defects in the images using automatic defect locating performed by the defect review tool.

12. The method of claim 1, wherein said aligning further comprises image processing.

13. The method of claim 1, further comprising selecting a bitmap pixel in inspection results produced by the wafer inspection tool for the wafer based on the design coordinates determined for one of the defects or the other defects and altering a process used to inspect the wafer based on the selected pixel.

14. A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for determining design coordinates for defects detected on a wafer, wherein the computer-implemented method comprises:

aligning a design for a wafer to images generated by a defect review tool at locations of defects on the wafer, wherein the defects are detected in multiple swaths scanned on the wafer by a wafer inspection tool prior to said aligning and prior to generation of the images by the defect review tool, wherein the locations of the defects at which the defect review tool generates the images are determined by the wafer inspection tool, wherein the defects comprise two or more first defects detected in a first of the multiple swaths and two or more second defects detected in a second of the multiple swaths, and wherein said aligning comprises overlaying portions of the design with the images generated by the defect review tool at the locations of the defects on the wafer;

determining a position of each of the defects in design coordinates based on results of said aligning;

separately determining at least a first defect position offset for the first of the multiple swaths, based on the design coordinates for each of the first defects and a position for each of the first defects determined by the wafer inspection tool, and a second defect position offset for the second of the multiple swaths, based on the design coordinates for each of the second defects and a position for each of the second defects determined by the wafer inspection tool; and

determining design coordinates for other defects detected in the multiple swaths by the wafer inspection tool by applying the first defect position offsets to positions of the other defects determined by the wafer inspection tool that were detected in the first of the multiple swaths and applying the second defect position offset to positions of the other defects determined by the wafer inspection tool that were detected in the second of the multiple swaths.

15. A system configured to determine design coordinates for defects detected on a wafer, comprising:

a defect review tool configured to generate images at locations of defects on the wafer, wherein the defects are detected in multiple swaths scanned on the wafer by a wafer inspection tool, wherein the locations of the defects at which the defect review tool generates the images are determined by the wafer inspection tool, and wherein the defects comprise two or more first defects detected in a first of the multiple swaths and two or more second defects detected in a second of the multiple swaths; and

a computer system configured for;

aligning a design for the wafer to the images, wherein the defects are detected by the wafer inspection tool prior to said aligning and prior to generation of the images by the defect review tool;

determining a position of each of the defects in design coordinates based on results of said aligning;

separately determining at least a first defect position offset for the first of the multiple swaths, based on the design coordinates for each of the first defects and a position for each of the first defects determined by the wafer inspection tool, and a second defect position offset for the second of the multiple swaths, based on the design coordinates for each of the second defects and a position for each of the second defects determined by the wafer inspection tool; and

determining design coordinates for other defects detected in the multiple swaths by the wafer inspection tool by applying the first defect position offsets to positions of the other defects determined by the wafer inspection tool that were detected in the first of multiple swaths and applying the second defect position offset to positions of the other defects determined by the wafer inspection tool that were detected in the second of the multiple swaths.

16. The system of claim 15, wherein the defects and the other defects comprise all defects detected on the wafer.

17. The system of claim 15, wherein said aligning, determining the position, separately determining at least the first and second defect position offsets, and determining the design coordinates produce design coordinates for the other defects that are accurate to within one pixel size of a pixel used by the wafer inspection tool when inspecting the wafer.

18. The system of claim 15, wherein said aligning, determining the position, separately determining at least the first and second defect position offsets, and determining the design coordinates produce design coordinates for the other defects that have an accuracy approximately equal to an accuracy of the defect review tool for determining a location of the defects within the images.

19. The system of claim 15, wherein the design is provided in a Graphical Data System (GDS) or Open Artwork System Interchange Standard (OASIS) file.

20. The system of claim 15, wherein the computer system is further configured for acquiring the design from an electronic design automation (EDA) tool.

21. The system of claim 15, wherein the defect review tool is a scanning electron microscope.

22. The system of claim 15, wherein the wafer inspection tool is an optical inspection tool.

23. The system of claim 15, wherein the wafer inspection tool is an electron beam-based inspection tool.

24. The system of claim 15, wherein the computer system is further configured for sampling the defects for which the images are generated by the defect review tool based on the swath in which the defects are detected.

25. The system of claim 15, wherein the detect review tool is further configured to locate the defects in the images using automatic defect locating.

26. The system of claim 15, wherein said aligning further comprises image processing.

27. The system of claim 15, wherein the computer system is further configured for selecting a bitmap pixel in inspection results produced by the wafer inspection tool for the wafer based on the design coordinates determined for one of the defects or the other defects and altering a process used to inspect the wafer based on the selected pixel.