Three dimension structure memory

• US 9,087,556 B2
• Filed: 08/12/2014
• Issued: 07/21/2015
• Est. Priority Date: 04/04/1997
• Status: Expired due to Fees

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J
• Primary Examiner(s): Lam, David
• Application Number:
  US14/457,515
• Publication Number:
  US 20140346649A1
• Time in Patent Office: 343 Days
• Field of Search: 257/777, 257/778, 257/685, 257/686, 365/51, 365/63, 365/72
• US Class Current: 1/1
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A circuit structure comprising:

a monocrystalline semiconductor layer of one piece;

a silicon-based dielectric layer formed on the monocrystalline semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile; and

circuitry supported by the monocrystalline semiconductor layer defining an integrated circuit die having an area, wherein the monocrystalline semiconductor layer extends throughout a substantial portion of the area of the integrated circuit die.

5. The circuit structure of claim 1, wherein the silicon-based dielectric layer is inherently flexible.

8. The circuit structure of one of claims 1, 2, and 4, wherein the circuit structure is capable of being made a substantially flexible circuit structure from the combination of thinning the monocrystalline semiconductor layer from a backside surface, polishing or smoothing the backside surface, and the silicon-based dielectric layer being inherently flexible.

9. The circuit structure of one of claims 1, 2, 4, 5, 6 and 7, wherein the circuitry comprises logic circuitry.

10. The circuit structure of claim 9, wherein the logic circuitry comprises one or more microprocessors.

11. The circuit structure of one of claims 1, 2, 4, 5, 6 and 7, wherein the circuitry comprises memory circuitry.

12. The circuit structure of claim 11, wherein the memory circuitry comprises at least one of DRAM and NAND memory cells.

13. The circuit structure of claim 11, wherein the memory circuitry comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

14. The circuit structure of one of claims 1, 2, 4, 5, 6 and 7, wherein the circuit structure comprises one or more memory circuit layers in a stacked relationship.

15. The circuit structure of claim 14, wherein at least one of the one or more memory circuit layers comprises an array memory cells.

16. The circuit structure of claim 15, wherein at least one of the one or more memory circuit layers comprises an array DRAM memory cells.

17. The circuit structure of claim 16, wherein at least one of the one or more memory circuit layers is vertically interconnected by vertical interconnections.

18. The circuit structure of claim 17, wherein at least one vertical interconnection comprises a conductive portion and a silicon based dielectric having a stress of less than 5×

10⁸ dynes/cm² tensile, and wherein the silicon based dielectric surrounds the conductive portion.

19. The circuit structure of claim 15, wherein the circuit structure comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

20. The circuit structure of one of claims 1, 2, 4, 5, 6 and 7, wherein the circuitry comprises one or more memory circuit layers and a logic circuit layer in a stacked relationship;

wherein a process technology used to make the logic circuit is different from a process technology used to make the memory circuit layers.

21. The circuit structure of claim 20, wherein at least one of the one or more memory circuit layers comprises an array of DRAM memory cells.

22. The circuit structure of claim 20, wherein at least one of the one or more memory circuit layers comprises an array of non-volatile memory cells.

23. The circuit structure of claim 22, wherein at least one of the non-volatile memory cells of the at least one or more memory circuit layers is vertically interconnected by vertical interconnections.

24. The circuit structure of claim 23, wherein at least one vertical interconnection comprises a conductive portion and a silicon based dielectric having a stress of less than 5×

10⁸ dynes/cm² tensile, and wherein the silicon based dielectric surrounds the conductive portion.

25. The circuit structure of claim 21, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

26. The circuit structure of one of claims 1, 2, 4, 5, 6 and 7, wherein said circuitry comprises:

a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship to form a stacked memory integrated circuit;

wherein at least a portion of the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit block stacks and configured for a plurality of said vertically interconnected circuit block stacks to independently perform memory operations.

27. The circuit structure of claim 26, wherein each of the plurality of vertically interconnected circuit block stacks comprises a memory array and an array of vertical interconnects interconnecting the vertically interconnected circuit block stack with the at least one control circuit layer.

28. The circuit structure of claim 26, wherein the at least one control circuit layer is configured to perform functional testing of at least part of the stacked memory integrated circuit.

29. The circuit structure of claim 28, wherein the functional testing by the at least one control circuit layer substantially reduces or eliminates the need for external testing of the stacked memory integrated circuit.

30. The circuit structure of claim 26, wherein the at least one control circuit layer is configured to perform refresh of at least part of the stacked memory integrated circuit.

31. The circuit structure of claim 26, wherein the at least one control circuit layer is configured to perform reconfiguration of at least part of the stacked memory integrated circuit.

32. The circuit structure of claim 26, wherein the at least one memory circuit layer comprises at least one of volatile and non-volatile memory cells.

33. The circuit structure of claim 26, wherein the at least one memory circuit layer comprises spare memory cells for replacement of defective memory cells.

34. The circuit structure of claim 26, further comprising spare or redundant vertical interconnections interconnecting the at least one control circuit layer and the at least one memory circuit layer.

35. The circuit structure of claim 26, wherein the at least one control circuit layer comprises memory error correction logic.

36. The circuit structure of claim 26, wherein the at least one control circuit layer comprises reconfiguration circuitry for reconfiguring the at least one memory circuit layer after manufacture of the stacked memory integrated circuit has been completed and during a useful life of the stacked memory integrated circuit.

37. The circuit structure of claim 26, wherein the at least one control circuit layer can be reconfigured to change an address used to access the at least one memory circuit layer.

38. The circuit structure of claim 26, wherein the at least one control circuit layer and the at least one memory circuit layer are bonded together by at least one thermal diffusion bond between the at least one control circuit layer and the at least one memory circuit layer.

39. The circuit structure of claim 26, wherein a process technology used to make the at least one control circuit is different from a process technology used to make the at least one memory circuit layer.

40. The circuit structure of claim 26, comprising:

a low stress silicon-based dielectric layer having a stress of about 5×

10⁸ dynes/cm² tensile or less formed on at least one of the at least one control circuit layer and the at least one memory circuit layer; and

at least one vertical interconnect formed within at least one of the at least one control circuit layer and the at least one memory circuit layer, the at least one vertical interconnect comprising a hole etched through a substrate of the at least one of the at least one control circuit layer and the at least one memory circuit layer and within the hole a conductive center portion and an insulating portion surrounding the conductive center portion, the insulating portion comprising dielectric material having a stress of about 5×

10⁸ dynes/cm² tensile or less.

41. The circuit structure of claim 26, wherein each of the at least one control circuit layer and the at least one memory circuit layer comprises a front side on which integrated circuitry is formed and a back side opposite the front side, wherein at least one of the at least one control circuit layer and the at least one memory circuit layer comprises a low stress silicon-based dielectric layer having a stress of about 5×

10⁸ dynes/cm² tensile or less formed on the back side.

42. The circuit structure of one of claims 1, 2, 4, 5, 6 and 7, further comprising at least one memory layer, and wherein the circuitry is a logic layer, the at least one memory layer and the logic layer forming a stacked integrated circuit memory.

43. The circuit structure of claim 42, wherein the logic layer and the at least one memory layer comprise a plurality of connections interior to the stacked integrated circuit memory for vertically routing bytes of data within the stacked integrated circuit memory during memory accesses.

44. The circuit structure of claim 42, wherein:

the logic layer comprises a memory controller circuit layer; and

, the at least one memory layer comprises a plurality of memory circuit layers each comprising at least one conductive layer and at least one low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile.

45. The circuit structure of claim 42, wherein the logic layer and at least one memory layer together further comprise:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry for coupling that data value to a corresponding one of the data lines in response to a gate control signal on a corresponding one of the gate lines;

circuitry that generates gate control signals in response to addresses based on a mapping of addresses to gate lines; and

circuitry that determines whether there are defective ones of the gate lines and reconfigures the mapping to eliminate references to the defective ones of the gate lines.

46. The circuit structure of claim 42, further comprising a three dimensional memory array that includes the at least one memory layer, the at least one memory layer comprising a plurality of interconnected layers of memory cells with at least one low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile adjacent to each of said layers of memory cells, wherein the vertical interconnections vertically interconnect the memory cells with the logic layer.

47. The circuit structure of claim 46, wherein the vertical interconnections comprise:

a plurality of interconnect conductors extending vertically through at least one of the plurality of interconnected layers of memory cells; and

, low stress dielectric that surrounds the plurality of interconnect conductors, wherein the low stress dielectric comprise silicon-based dielectric with a stress of less than 5×

10⁸ dynes/cm² tensile.

48. The circuit structure of claim 42, wherein the at least one memory layer is formed with a low stress dielectric material that is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and has a stress of less than 5×

10⁸ dynes/cm² tensile.

49. The circuit structure of claim 42, wherein the logic layer and the at least one memory layer together further comprise:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry to couple that data value to a corresponding one of said data lines in response to a gate control signal on a corresponding one of said gate lines;

circuitry that generates gate control signals in response to addresses based on a mapping of addresses to gate lines; and

circuitry that determines at least one of whether there are defective ones of said memory cells and whether there are defective ones of the gate lines and reconfigures the mapping for at least one of eliminating references to the corresponding ones of the gate lines for said defective ones of said memory cells and eliminating references to the defective ones of the gate lines.

50. The circuit structure of claim 42, comprising:

logic on the logic layer for initiating memory accesses; and

vertical interconnections configured to route bytes of data of a memory access interior to the circuit structure between the logic layer and at least one memory location on the at least one memory layer.

51. The circuit structure of claim 50, comprising test logic on the logic layer to perform testing of the at least one memory layer via the vertical interconnections.

52. The circuit structure of claim 50, comprising error correction logic on the logic layer to perform error correction of the bytes of data from the at least one memory layer via the vertical interconnections.

99. The circuit structure of claim 12, wherein the memory circuitry comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

100. The circuit structure of claim 16, wherein the circuit structure comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

101. The circuit structure of claim 17, wherein the circuit structure comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

102. The circuit structure of claim 18, wherein the circuit structure comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

103. The circuit structure of claim 22, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

104. The circuit structure of claim 23, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

105. The circuit structure of claim 24, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

2. A circuit structure comprising:

a monocrystalline semiconductor layer of one piece;

a silicon-based dielectric layer formed on the monocrystalline semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile;

circuitry supported by the monocrystalline semiconductor layer; and

edges that define the circuit structure'"'"'s size in area;

wherein the monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges.

6. The circuit structure of claim 2, wherein the silicon-based dielectric layer is inherently flexible.

3. A circuit die comprising:

a monocrystalline semiconductor layer of one piece;

a silicon-based dielectric layer formed on the monocrystalline semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile;

circuitry supported by the monocrystalline semiconductor layer; and

edges that define the circuit die'"'"'s size in area;

wherein the monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges.

53. The circuit die of claim 3, wherein the silicon-based dielectric layer is inherently flexible.

54. The circuit die of claim 3, wherein the circuit die is capable of being made a substantially flexible circuit die from the combination of thinning the monocrystalline semiconductor layer from a backside surface, polishing or smoothing the backside surface, and the silicon-based dielectric layer being inherently flexible.

55. The circuit die of one of claims 3, 53 and 54, wherein the circuitry comprises logic circuitry.

56. The circuit die of claim 55, wherein the logic circuitry comprises one or more microprocessors.

57. The circuit die of one of claims 3, 53 and 54, wherein the circuitry comprises memory circuitry.

58. The circuit die of claim 57, wherein the memory circuitry comprises at least one of DRAM and NAND memory cells.

59. The circuit die of claim 57, wherein the memory circuitry comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

60. The circuit die of one of claims 3, 53 and 54, wherein the circuit die comprises one or more memory circuit layers in a stacked relationship.

61. The circuit die of claim 60, wherein one of the one or more memory circuit layers comprise an array memory cells.

62. The circuit die of claim 61, wherein one of the one or more memory circuit layers comprise an array DRAM memory cells.

63. The circuit die of claim 62, wherein at least one of the one or more memory circuit layers are vertically interconnected by vertical interconnections.

64. The circuit die of claim 63, wherein at least one vertical interconnection comprises a conductive portion and a silicon based dielectric having a stress of less than 5×

10⁸ dynes/cm² tensile, and wherein the silicon based dielectric surrounds the conductive portion.

65. The circuit die of claim 61, wherein the circuit die comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

66. The circuit die of claim 3, wherein the circuitry comprises one or more memory circuit layers and a logic circuit layer in a stacked relationship;

and, wherein a process technology used to make the logic circuit is different from a process technology used to make the memory circuit layers.

67. The circuit die of claim 66, wherein at least one of the one or more memory circuit layers comprises an array DRAM memory cells.

68. The circuit die of claim 66, wherein at least one of the one or more memory circuit layers comprises an array non-volatile memory cells.

69. The circuit die of claim 68, wherein one of the non-volatile memory cells of the at least one or more memory circuit layers are vertically interconnected by vertical interconnections.

70. The circuit die of claim 69, wherein at least one vertical interconnection comprises a conductive portion and a silicon based dielectric having a stress of less than 5×

10⁸ dynes/cm² tensile, and wherein the silicon based dielectric surrounds the conductive portion.

71. The circuit die of claim 67, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

72. The circuit die of one of claims 3 and 53, wherein said circuitry comprises:

a plurality of circuit layers comprising at least one control circuit layer and at least one memory circuit layer arranged in a stacked relationship to form a stacked memory integrated circuit;

wherein at least a portion of the control and memory circuit layers of the stacked memory integrated circuit are partitioned into a plurality of vertically interconnected circuit block stacks and configured for a plurality of said vertically interconnected circuit block stacks to independently perform memory operations.

73. The circuit die of claim 72, wherein each of the plurality of vertically interconnected circuit block stacks comprises a memory array and an array of vertical interconnects interconnecting the vertically interconnected circuit block stack with the at least one control circuit layer.

74. The circuit die of claim 72, wherein the at least one control circuit layer is configured to perform functional testing of at least part of the stacked memory integrated circuit.

75. The circuit die of claim 74, wherein the functional testing by the at least one control circuit layer substantially reduces or eliminates the need for external testing of the stacked memory integrated circuit.

76. The circuit die of claim 72, wherein the at least one control circuit layer is configured to perform refresh of at least part of the stacked memory integrated circuit.

77. The circuit die of claim 72, wherein the at least one control circuit layer is configured to perform reconfiguration of at least part of the stacked memory integrated circuit.

78. The circuit die of claim 72, wherein the at least one memory circuit layer comprises at least one of volatile and non-volatile memory cells.

79. The circuit die of claim 72, wherein the at least one memory circuit layer comprises spare memory cells for replacement of defective memory cells.

80. The circuit die of claim 72, further comprising spare or redundant vertical interconnections interconnecting the at least one control circuit layer and the at least one memory circuit layer.

81. The circuit die of claim 72, wherein the at least one control circuit layer comprises memory error correction logic.

82. The circuit die of claim 72, wherein the at least one control circuit layer comprises reconfiguration circuitry for reconfiguring the at least one memory circuit layer after manufacture of the stacked memory integrated circuit has been completed and during a useful life of the stacked memory integrated circuit.

83. The circuit die of claim 72, wherein the at least one control circuit layer can be reconfigured to change an address used to access the at least one memory circuit layer.

84. The circuit die of claim 72, wherein the at least one control circuit layer and the at least one memory circuit layer are bonded together by at least one thermal diffusion bond between the at least one control circuit layer and the at least one memory circuit layer.

85. The circuit die of claim 72, wherein a process technology used to make the at least one control circuit is different from a process technology used to make the at least one memory circuit layer.

86. The circuit die of claim 72, comprising:

a low stress silicon-based dielectric layer having a stress of about 5×

10⁸ dynes/cm² tensile or less formed on at least one of the at least one control circuit layer and the at least one memory circuit layer; and

at least one vertical interconnect formed within at least one of the at least one control circuit layer and the at least one memory circuit layer, the at least one vertical interconnect comprising a hole etched through a substrate of the at least one of the at least one control circuit layer and the at least one memory circuit layer and within the hole a conductive center portion and an insulating portion surrounding the conductive center portion, the insulating portion comprising dielectric material having a stress of about 5×

10⁸ dynes/cm² tensile or less.

87. The circuit die of claim 72, wherein each of the at least one control circuit layer and the at least one memory circuit layer comprises a front side on which integrated circuitry is formed and a back side opposite the front side, wherein at least one of the at least one control circuit layer and the at least one memory circuit layer comprises a low stress silicon-based dielectric layer having a stress of about 5×

10⁸ dynes/cm² tensile or less formed on the back side.

88. The circuit die of one of claims 3 and 53, further comprising at least one memory layer, and wherein the circuitry is a logic layer, the at least one memory layer and the logic layer together forming a stacked integrated circuit memory.

89. The circuit die of claim 88, wherein the logic layer and the at least one memory layer comprise a plurality of connections interior to the stacked integrated circuit memory for vertically routing bytes of data within the stacked integrated circuit memory during memory accesses.

90. The circuit die of claim 88, wherein:

the logic layer comprises a memory controller circuit layer; and

, the at least one memory layer comprises a plurality of memory circuit layers each comprising at least one conductive layer and at least one low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile.

91. The circuit die of claim 88, wherein the logic layer and at least one memory layer together further comprise:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry for coupling that data value to a corresponding one of the data lines in response to a gate control signal on a corresponding one of the gate lines;

circuitry that generates gate control signals in response to addresses based on a mapping of addresses to gate lines; and

circuitry that determines whether there are defective ones of the gate lines and reconfigures the mapping to eliminate references to the defective ones of the gate lines.

92. The circuit die of claim 88, further comprising a three dimensional memory array that includes the at least one memory layer and the at least one memory layer comprising a plurality of interconnected layers of memory cells with at least one low stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile adjacent to each of said layers of memory cells, wherein vertical interconnections vertically interconnect the memory cells with the logic layer.

93. The circuit die of claim 92, wherein the vertical interconnections comprise:

a plurality of interconnect conductors extending vertically through at least one of the plurality of interconnected layers of memory cells; and

, low stress dielectric surrounds the plurality of interconnect conductors, wherein the low stress dielectric comprise silicon-based dielectric with a stress of less than 5×

10⁸ dynes/cm² tensile.

94. The circuit die of claim 88, wherein the at least one memory layer is formed with a low stress dielectric material that is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and has a stress of less than 5×

10⁸ dynes/cm² tensile.

95. The circuit die of claim 88, wherein the logic layer and the at least one memory layer together further comprise:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry to couple that data value to a corresponding one of said data lines in response to a gate control signal on a corresponding one of said gate lines;

circuitry that generates gate control signals in response to addresses based on a mapping of addresses to gate lines; and

circuitry that determines at least one of whether there are defective ones of said memory cells and whether there are defective ones of the gate lines and reconfigures the mapping for at least one of eliminating references to the corresponding ones of the gate lines for said defective ones of said memory cells and eliminating references to the defective ones of the gate lines.

96. The circuit die of claim 88, comprising:

logic on the logic layer for initiating memory accesses; and

vertical interconnections configured to route bytes of data of a memory access interior to the circuit die between the logic layer and at least one memory location on the at least one memory layer.

97. The circuit die of claim 96, comprising test logic on the logic layer to perform testing of the at least one memory layer via the vertical interconnections.

98. The circuit die of claim 96, comprising error correction logic on the logic layer to perform error correction of the bytes of data from the at least one memory layer via the vertical interconnections.

106. The circuit die of claim 58, wherein the memory circuitry comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

107. The circuit die of claim 62, wherein the circuit die comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

108. The circuit die of claim 63, wherein the circuit die comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

109. The circuit die of claim 64, wherein the circuit die comprises two or more memory circuit layers in a stacked relationship, and at least two of the one or more memory circuit layers are bonded together by at least one thermal diffusion bond.

110. The circuit die of claim 68, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

111. The circuit die of claim 69, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

112. The circuit die of claim 70, wherein the logic circuit layer comprises at least one of refresh circuitry, error correction circuitry, reconfiguration circuitry and test circuitry.

4. A circuit structure comprising:

a monocrystalline semiconductor layer of one piece;

a silicon-based dielectric layer formed on the monocrystalline semiconductor layer and having a stress of less than 5×

10⁸ dynes/cm² tensile; and

circuitry supported by the monocrystalline semiconductor layer;

wherein the monocrystalline semiconductor layer extends in one piece from edge to edge of the dielectric layer.

7. The circuit structure of claim 4, wherein the silicon-based dielectric layer is inherently flexible.