Phase change memory device having multi-level and method of driving the same

• US 9,087,575 B2
• Filed: 09/23/2014
• Issued: 07/21/2015
• Est. Priority Date: 06/15/2009
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Hae Chan, Lee, Se Ho
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/494,403
• Publication Number:
  US 20150043268A1
• Time in Patent Office: 301 Days
• Field of Search: 365/148, 365/189.03, 365/189.15, 365/189.16
• US Class Current: 1/1
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors

Abstract

A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Claims

1. A method of driving a phase change memory device that includes bit lines, variable resistors that are electrically connected to the bit lines, first switching elements that are connected to the variable resistors, second switching elements that are electrically connected to the first switching elements, and memory cells including first word lines that control the first switching elements and second word lines that control second switching elements, the method of driving a phase change memory comprising:

when writing the memory cells, grounding the first word lines and writing a first set state and a first reset state by applying a set voltage and a reset voltage preset via the bit lines when the second word lines are floating, and

floating the first word line and writing a second set state and a second reset state by applying the set voltage and the reset voltage via the bit lines when the second word lines are grounded.

2. The method of driving a phase change memory device of claim 1, further comprising:

when reading the memory cell, applying first to third read voltages having different levels than a holding voltage or less than a threshold voltage while not causing the variable resistors to change phase, such that the first to third read voltages are applied through the bit lines to determine each level based on the input read voltage.

3. The method of driving a phase change memory device of claim 1, further comprising:

when reading the memory cell,

applying a first read voltage of a holding voltage or less that is a threshold voltage through the bit lines to divide a set group and a reset group while not causing the variable resistors to change phase;

when being divided into the set group, applying a second read voltage having a voltage lower than the first read voltage through the bit line to divide the first set state and the second set state; and

when being divided into the reset group, applying a third read voltage having a larger voltage than that of the first read voltage through the bit line to divide the first reset state and the second reset state.

4. The method of driving a phase change memory device of claim 3, wherein the dividing the set group and the reset group and the dividing the first set state, the second set state, the first reset state and second reset state are performed when different word lines are grounded.

5. The method of driving a phase change memory device of claim 4, wherein dividing the set group and the reset group grounds the first word line and floats the second word line.

6. The method of driving a phase change memory device of claim 5, wherein dividing the first set state, the second set state, the first reset state and the second reset state floats the first word line and grounds the second word line.

7. The method of driving a phase change memory device of claim 3, wherein the third read voltage is positioned in a range that is larger than the holding voltage and smaller than an upper voltage limit,

wherein the upper voltage limit is a maximum voltage where phase change occurs to the variable resistors.