Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

• US 9,087,580 B2
• Filed: 09/26/2011
• Issued: 07/21/2015
• Est. Priority Date: 08/22/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Vanthu
• Assistant Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US13/244,812
• Publication Number:
  US 20120106234A1
• Time in Patent Office: 1,394 Days
• Field of Search: 365/148, 365/163, 365/228, 365/185.08, 365/189.2, 257/316, 257/E29.3
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 : Material having simple binary metal oxide structure
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/10 : Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/32 : of the bipolar type
• CPC Class Codes: H10B 63/80 : Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 : between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Claims

1. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions;

wherein said capacitorless transistor and said non-volatile memory are connected in series;

wherein current flowing to said resistance change element flows through said floating body;

wherein one of said predetermined conditions comprises loss of power to said cell;

wherein said cell is configured to perform a shadowing process when said data in said floating body is loaded into and stored in said nonvolatile memory;

wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and

wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

2. The semiconductor memory cell of claim 1, wherein said resistance change element comprises a phase change material.

3. The semiconductor memory cell of claim 1, wherein said resistance change element comprises a metal-oxide-metal system.

4. The semiconductor memory cell of claim 1 wherein one of said conditions comprises an instruction to back up said data stored in said floating body.

5. The semiconductor memory cell of claim 1, wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein intentional power loss is predetermined to conserve power.

6. The semiconductor memory cell of claim 1, wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said high resistance state.

7. The semiconductor memory cell of claim 1, wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said low resistance state.

8. The semiconductor memory cell of claim 1, arranged in a semiconductor memory array comprising a plurality of said semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows.

9. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions;

wherein said capacitorless transistor and said non-volatile memory are connected in series;

wherein one of said predetermined conditions comprises loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory;

wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and

wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

10. The semiconductor memory cell of claim 9, wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said high resistance state.

11. The semiconductor memory cell of claim 9, wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said low resistance state.

12. A semiconductor memory cell comprising:

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and

a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body upon unintentional power loss or intentional power loss to said cell;

wherein said capacitorless transistor and said non-volatile memory are connected in series;

wherein said cell is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory;

wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and

wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.