Pre-charging method applied in dynamic random access memories

• US 9,087,604 B1
• Filed: 04/13/2014
• Issued: 07/21/2015
• Est. Priority Date: 04/13/2014
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Derner, Scott, Ingalls, Charles, Kirsch, Howard, Kim, Tae
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/251,641
• Time in Patent Office: 464 Days
• Field of Search: 365/203, 365/210.1, 365/210.12
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A pre-charging method applied in DRAM which includes steps of: enabling wordlines in an active array and an reference array; disabling the wordlines in the active array; equilibrating digital lines in the active array and the reference array to half of a power supply voltage; storing the half of the power supply voltage in reference cells of the reference array; disabling the wordlines in the reference array; pre-charging the digital lines in the active array and the reference array to the power supply voltage; and enabling the wordlines in the active array and the reference array at the same time.

Claims

1. A pre-charging method applied in dynamic random access memories (DRAM), comprising:

disabling wordlines in an active array;

equilibrating digital lines in the active array and an reference array to half of a power supply voltage;

disabling wordlines in the reference array; and

pre-charging the digital lines in the active array and the reference array to the power supply voltage.

2. The pre-charging method of claim 1, further comprising:

storing the half of the power supply voltage in reference cells of the reference array.

3. The pre-charging method of claim 2, wherein the step of disabling wordlines in the reference array is executed after the step of disabling the wordlines in the active array for a predetermined time period.

4. The pre-charging method of claim 3, wherein the step of storing the half of the power supply voltage in the reference cells of the reference array is executed in the predetermined time period.

5. The pre-charging method of claim 1, further comprising:

enabling the wordlines in the active array and the reference array.

6. The pre-charging method of claim 5, wherein the step of disabling the wordlines in the active array is executed after the step of enabling the wordlines in the active array and the reference array.

7. The pre-charging method of claim 1, wherein the step of disabling the wordlines in the reference array is executed after the step of equilibrating the digital lines in the active array and the reference array to half of the power supply voltage.

8. The pre-charging method of claim 1, wherein the step of pre-charging the digital lines in the active array and the reference array to the power supply voltage is executed after the step of disabling the wordlines in the reference array.

9. The pre-charging method of claim 1, further comprising:

enabling wordlines in the active array and the reference array at the same time.

10. The pre-charging method of claim 9, the step of enabling the wordlines in the active array and the reference array at the same time is executed after the step of pre-charging the digital lines in the active array and the reference array to the power supply voltage.