CMOS with dual raised source and drain for NMOS and PMOS

• US 9,087,741 B2
• Filed: 07/11/2011
• Issued: 07/21/2015
• Est. Priority Date: 07/11/2011
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Haran, Balasubramanian S.
• Primary Examiner(s): Sun, Yu-Hsi D
• Assistant Examiner(s): Singal, Ankush
• Application Number:
  US13/179,990
• Publication Number:
  US 20130015525A1
• Time in Patent Office: 1,471 Days
• Field of Search: 257/347, 257/E29.285, 257/E21.415, 257/E29.02, 257/E21.632, 438/154, 438/166
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 : adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 : Silicon carbide
• CPC Class Codes: H01L 29/161 : including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/167 : further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/41783 : Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/665 : using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 : using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

Claims

1. A method of forming a CMOS structure, the method comprising:

providing a silicon-on-insulator substrate having a first substrate surface in a first region and a second substrate surface in a second region, wherein the first substrate surface and the second substrate surface are isolated by a shallow trench isolation;

forming a first gate stack on the first substrate surface and a second gate stack on the second substrate surface;

forming a first insulating layer on all exposed surfaces in the first and second regions;

etching the first insulating layer in the second region to form insulating spacers on sidewalls of the second gate stack;

forming raised epitaxial source and drain layers on the second substrate surface;

forming a second insulating layer on all exposed surfaces in the first and second regions;

removing the second insulating layer in the first region to expose the first insulating layer;

etching the first insulting layer in order to form insulating spacers on sidewalls of the first gate stack and expose the first substrate surface;

forming undoped raised epitaxial source and drain layers on the first substrate surface;

implanting a dopant into the raised source and drain layers on the first substrate surface;

removing the second insulating layer in the second region, leaving the insulating spacers on the sidewalls of the first and second gate stacks;

if the raised source and drain layers on the second substrate surface are undoped, implanting a dopant into the raised source and drain layers on the second substrate surface; and

forming a second set of spacers between the raised source and drain layers and the insulating spacers on the sidewalls of the first and second gate stacks; and

with the insulating spacers still remaining on the sidewalls of the first and second gate stacks, forming silicide contacts on the source and drain layers in both the first and second regions and on the first and second gate stacks.

2. The method of claim 1, wherein the step of removing the second insulating layer from the first region is carried out by using photolithography to expose the second insulating layer in the first region and using a wet etch to remove the second insulating layer.