Structure and method for a high-K transformer with capacitive coupling

• US 9,087,838 B2
• Filed: 10/25/2011
• Issued: 07/21/2015
• Est. Priority Date: 10/25/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Lin, Yu-Ling, Kuo, Chin-Wei, Chen, Ho-Hsiang, Jeng, Min-Chie
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): Joy, Jeremy
• Application Number:
  US13/280,786
• Publication Number:
  US 20130099352A1
• Time in Patent Office: 1,365 Days
• Field of Search: 257/531, 257/E21.022
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having an integrated circuit (IC) device;

an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and

a transformer disposed on the semiconductor substrate and integrated in the interconnect structure, wherein the transformer includes;

a first conductive feature,

a second conductive feature inductively coupled with the first conductive feature,

a third conductive feature electrically connected to the first conductive feature, and

a fourth conductive feature electrically connected to the second conductive feature, wherein the third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer, and

wherein the first conductive feature is electrically connected with first two ports and is further configured to form a first coil element, and

wherein the second conductive feature is electrically connected with second two ports and further configured to form a second coil element.

2. The semiconductor device of claim 1, wherein the first coil element includes multiple turns and the second coil element includes multiple turns.

3. The semiconductor device of claim 1, wherein:

the third conductive feature has at least two ends configured to be electrically floating; and

the fourth conductive feature has at least two ends configured to be electrically floating.

4. The semiconductor device of claim 1, wherein:

the interconnect structure includes a plurality of metal layers having a first metal layer, a second metal layer, and a third metal layer;

the first and second conductive features substantially belong to the first metal layer;

the third conductive feature belongs to the second metal layer;

the fourth conductive feature belongs to the third metal layer; and

the first, second, third, and fourth conductive features are substantially aligned in a direction perpendicular to the semiconductor substrate to enhance respective inductive and capacitive couplings.

5. The semiconductor device of claim 4, wherein the third conductive feature is electrically connected to the first conductive feature through a first via feature between the first and second metal layers.

6. The semiconductor device of claim 5, wherein the fourth conductive feature is electrically connected to the second conductive feature though a second via feature between the first and third metal layers.

7. The semiconductor device of claim 4, wherein:

the second metal layer is underlying the first metal layer; and

the third metal layer is underlying the second metal layer.

8. The semiconductor device of claim 4, wherein:

the second metal layer is underlying the first metal layer; and

the third metal layer is overlying the first metal layer.

9. The semiconductor device of claim 1, further comprising a fifth conductive feature electrically connected to the third conductive feature to further enhance capacitive coupling.

10. An integrated circuit, comprising:

a transformer disposed on a substrate, including;

a first inductive coupling feature having first two ports;

a second inductive coupling feature having second two ports; and

a first capacitive coupling feature electrically connected to the first inductive coupling feature and having at least first two ends configured to be floating, wherein the first and second inductive coupling features are configured to be inductively coupled, and the first capacitive coupling feature is configured to be capacitively coupled with the second inductive coupling feature.

11. The integrated circuit of claim 10, further comprising a second capacitive coupling feature electrically connected to the second inductive coupling feature and having at least second two ends configured to be floating, wherein the second capacitive coupling feature is configured to be capacitively coupled with the first inductive coupling feature.

12. The integrated circuit of claim 11, wherein the first and second inductive coupling features and the first and second capacitive coupling features are substantially aligned within a same region of the substrate in a top view toward the substrate to enhance corresponding inductive and capacitive couplings.

13. The integrated circuit of claim 11, further comprising an interconnect structure having a plurality of metal layers disposed on the substrate, wherein the transformer is integrated in the interconnect structure.

14. The integrated circuit of claim 13, wherein the first and second inductive coupling features are substantially configured in a same metal layer of the interconnect structure.

15. The integrated circuit of claim 11, wherein:

the second capacitive coupling feature is underlying the first and second inductive coupling features; and

the second capacitive coupling feature is further configured to provide a shielding function.

16. The integrated circuit of claim 11, wherein both the first and second capacitive coupling features are underlying the first inductive coupling feature and are overlying the second inductive coupling feature.

17. The integrated circuit of claim 16, further comprising:

an additional substrate configured such that the transformer is distributed between the substrate and the additional substrate; and

a through silicon via (TSV) interposer disposed between the substrate and the additional substrate, wherein various features of the transformer are coupled at least partially the TSV interposer.

18. The integrated circuit of claim 11, wherein one of the first inductive feature, the second inductive feature, the first capacitive feature, and the second capacitive feature is connected to one of a voltage source and a ground line.

19. A circuit device:

a substrate;

a first conductive feature disposed on the substrate;

a second conductive feature disposed on the substrate and within the first conductive feature;

a third conductive feature disposed on the substrate, wherein the third conductive feature is electrically coupled to the first conductive feature, wherein the third conductive feature is capacitively coupled to the second conductive feature, and wherein the third conductive feature has at least two ends configured to be electrically floating.

20. The circuit device of claim 19, further comprising:

a fourth conductive feature disposed on the substrate, wherein the fourth conductive feature is electrically coupled to the second conductive feature, and wherein the fourth conductive feature is capacitively coupled to the first conductive feature.

21. The circuit device of claim 20, wherein the fourth conductive feature has at least two ends configured to be electrically floating.