Semiconductor device

• US 9,087,886 B2
• Filed: 12/18/2013
• Issued: 07/21/2015
• Est. Priority Date: 04/08/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ju-Youn
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Rahim, Nilufa
• Application Number:
  US14/132,306
• Publication Number:
  US 20140299939A1
• Time in Patent Office: 580 Days
• Field of Search: 257/407, 257/412, 257/E21.626, 257/E21.64, 257/369, 438/183, 438/199, 438/585, 438/634, 438/696, 438/592
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Provided are a semiconductor device and a fabricating method of the semiconductor device. The semiconductor device may include an interlayer dielectric film formed on a substrate and including a trench, a gate insulating film formed in the trench, a first work function control film formed on the gate insulating film of the trench along bottom and sidewalls of the trench, a first metal gate pattern formed on the first work function control film of the trench and filling a portion of the trench, and a second metal gate pattern formed on the first metal gate pattern of the trench, the second metal gate pattern different from the first metal gate pattern.

Claims

1. A semiconductor device comprising:

an interlayer dielectric film formed on an upper surface of a substrate, the interlayer dielectric film including a trench;

a gate insulating film formed in the trench;

a work function control film formed on the gate insulating film of the trench along bottom and sidewalls of the trench;

a first metal gate pattern on the work function control film of the trench and filling a portion of the trench;

a second metal gate pattern on the first metal gate pattern of the trench, the second metal gate pattern different from the first metal gate pattern; and

an adhesive film disposed between the second metal gate pattern and the work function control film and between the second metal gate pattern and the first metal gate pattern,

wherein a distance from the upper surface of the substrate to an uppermost surface of the second metal gate pattern is greater than a distance from the upper surface of the substrate to an uppermost surface of the first metal gate pattern.

2. The semiconductor device of claim 1, wherein the work function control film includes an inclined uppermost surface defining an acute angle with respect to the sidewalls of the trench.

3. The semiconductor device of claim 2, wherein a top surface of the first metal gate pattern is positioned below the inclined uppermost surface of the work function control film.

4. The semiconductor device of claim 1, wherein the first metal gate pattern has a thickness in a range between 10 Å

to 100 Å

.

5. The semiconductor device of claim 1, wherein the semiconductor device is an NMOS transistor, the first metal gate pattern is at least one element selected from the group consisting of aluminum (Al), tungsten (W) and titanium (Ti), and the second metal gate pattern is another at least one element selected from the group consisting of Al, W and Ti.

6. The semiconductor device of claim 1, wherein when the second metal gate pattern is made of tungsten (W), the adhesive film is made of titanium nitride (TiN), and when the second metal gate pattern is made of aluminum (Al), the adhesive film is made of titanium (Ti) or titanium nitride (TiN).

7. The semiconductor device of claim 1, wherein the semiconductor device is a fin type transistor.

8. A semiconductor device comprising:

an interlayer dielectric film formed on an upper surface of a substrate, the interlayer dielectric film including a first trench and a second trench spaced apart from the first trench;

an NMOS transistor having a first replacement metal gate formed in the first trench; and

a PMOS transistor having a second replacement metal gate formed in the second trench, wherein the first replacement metal gate comprises;

a work function control film along a bottom and sidewalls of the first trench;

a first metal gate pattern on the work function control film of the first trench and filling a portion of the first trench; and

a second metal gate pattern on the first metal gate pattern of the first trench, the second metal gate pattern different from the first metal gate pattern,

wherein the work function control film of the first replacement metal gate is a first work function control film comprising a first material, and

wherein the second replacement metal gate comprises;

a second work function control film comprising a second material different from the first material, the second work function control film formed along bottom and sidewalls of the second trench,

a third work function control film comprising the first material, the third work function control film formed on the P type work function control film;

a third metal gate pattern formed on the third work function control film in the second trench and filling a portion of the second trench; and

a fourth metal gate pattern formed on the third metal gate pattern in the second trench, the fourth metal gate pattern different from the third metal gate pattern.

9. A semiconductor device comprising:

an interlayer dielectric film on an upper surface of a substrate, the interlayer dielectric film including a trench;

a gate insulating film on a bottom and sidewall surfaces of the trench;

a work function control film on the gate insulating film comprising a chamfered uppermost surface at an opening of the trench defining an acute angle with respect to the sidewall surfaces of the trench;

a first metal gate pattern on the work function control film and filling a portion of the trench; and

a second metal gate pattern on the first metal gate pattern, the second metal gate pattern comprising a different composition from a composition of the first metal gate pattern,

wherein a distance from the upper surface of the substrate to an uppermost surface of the second metal gate pattern is greater than a distance from the upper surface of the substrate to an uppermost surface of the first metal gate pattern,

further comprising an adhesive film between the second metal gate pattern and the work function control film and between the second metal gate pattern and the first metal gate pattern, the adhesive film including a chamfered uppermost surface defining an acute angle with respect to the sidewall surfaces of the trench, wherein the chamfered uppermost surface of the adhesive film is on the chamfered uppermost surface of the work function control film.

10. The semiconductor device of claim 9, wherein the work function control film is a first work function control film comprising a first material, wherein the semiconductor device further comprises a second work function control film between the gate insulating film and the first work function control film, the second work function control film comprising a second material different from the first material, wherein the second work function control film includes a chamfered uppermost surface defining an acute angle with respect to the sidewall surfaces of the trench, and

wherein the chamfered uppermost surface of the second work function control film and the chamfered uppermost surface of the first work function control film are continuous.