Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

• US 9,087,899 B2
• Filed: 03/05/2014
• Issued: 07/21/2015
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Brindle, Christopher N., Deng, Jie, Genc, Alper, Yang, Chieh-Kai
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US14/198,315
• Publication Number:
  US 20140312422A1
• Time in Patent Office: 503 Days
• Field of Search: 257/347, 257/352, 257/E29.422, 257/105, 257/40, 257/402, 257/403, 257/59, 455/333, 455/425, 455/550.1
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

Claims

1. An accumulated charge control (ACC) floating body metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a gate;

a drain;

a source;

a body, wherein the body comprises a gate modulated conductive channel between the source and the drain;

a gate oxide layer positioned between the gate and the body; and

an accumulated charge sink (ACS) region operatively coupled to the body, wherein the ACS region comprises an implant region disposed within or adjacent the body;

wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in an accumulated charge regime and wherein accumulated charge is removed or controlled by applying a bias voltage to the ACS region,

wherein the gate modulated conductive channel, source, and drain have carriers of identical polarity when the MOSFET is biased to operate in an on-state and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in a off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain, and gate modulated conductive channel, and

wherein the MOSFET has an operational body to gate bias voltage and the ACS region has parasitic MOS capacitance turned on at a body to gate bias voltage threshold and wherein the implant region is doped with selected dopant materials and at selected dopant levels to provide that the parasitic MOS capacitance is turned on at a body to gate bias voltage threshold less than or greater than the operational body to gate bias voltage.

2. The ACC MOSFET according to claim 1, wherein the gate modulated conductive channel comprises material doped with a first dopant and the ACS region comprises material doped with a second dopant, wherein the second dopant is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

3. The ACC MOSFET according to claim 1, wherein the gate modulated conductive channel comprises material doped with a dopant at a first doping level and the ACS region comprises material doped with the dopant at a second doping level, wherein the second doping level is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

4. The ACC MOSFET according to claim 1, wherein the gate modulated conductive channel comprises material doped with a first dopant at a first doping level and the ACS region comprises material doped with a second dopant at a second doping level, wherein the second dopant and second doping level are selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

5. The ACC MOSFET according to claim 1, further comprising an electrical contact region, wherein the electrical contact region and the ACS region are coextensive.

6. The ACC MOSFET according to claim 1, further comprising an electrical contact region positioned proximate to and in electrical contact with the ACS region, wherein the electrical contact region facilitates electrical coupling to the ACS region and wherein the electrical contact region comprises same material as material comprising the ACS region.

7. The ACC MOSFET according to claim 1, further comprising an electrical contact region positioned proximate to and in electrical contact with the ACS region, wherein the electrical contact region facilitates electrical coupling to the ACS region and wherein the electrical contact region comprises different material from material comprising the ACS region.

8. The ACC MOSFET according to claim 7, wherein the electrical contact region comprises metal.

9. The ACC MOSFET according to claim 1, wherein the ACS region is electrically coupled to the gate.

10. The ACC MOSFET according to claim 1, wherein the ACC MOSFET comprises an NMOSFET device, and wherein the accumulated charge comprises holes having “

P”

polarity.

11. The ACC MOSFET according to claim 10, wherein the NMOSFET comprises an enhancement mode NMOSFET.

12. The ACC MOSFET according to claim 11, wherein the NMOSFET comprises a depletion mode NMOSFET.

48. The ACC MOSFET according to claim 1, wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology.

13. An accumulated charge control floating body MOSFET (ACC MOSFET) adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising:

a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is operated in a non-conducting or near non-conducting state and charge accumulates within the body in a region proximate and underneath the gate oxide layer;

b) a first accumulated charge sink (ACS) region positioned proximate a first distal end of the floating body, wherein the first ACS region is in electrical communication with the floating body, and wherein, when the MOSFET is operated in the accumulated charge regime, a first ACS bias voltage (V_ACS1) is applied to the first ACS region to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the first ACS region;

c) a second accumulated charge sink (ACS) region positioned proximate a second distal end of the floating body, wherein the second ACS region is in electrical communication with the floating body and wherein, when the MOSFET is operated in the accumulated charge regime, a second ACS bias voltage (V_ACS2) is applied to the second ACS region to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the second ACS region;

d) a first electrical contact region positioned proximate to and in electrical communication with the first ACS region, wherein the electrical contact region facilitates electrical coupling to the first ACS region;

e) a second electrical contact region positioned proximate to and in electrical communication with the second ACS region, wherein the electrical contact region facilitates electrical coupling to the second ACS region; and

f) a structure electrically connecting the first electrical contact region with the second electrical contact region, wherein the structure providing the electrical connection between the first electrical contact region and the second electrical contact region cancels or mostly cancels parasitic capacitance between the floating body and the gate.

14. The ACC MOSFET according to claim 13, wherein the electrical communication between the first electrical contact region and the second electrical contact region is provided by a path having a path impedance.

15. The ACC MOSFET according to claim 14, wherein the first ACS region couples to the floating body at a first ACS impedance and the second ACS region couples to the floating body at a second ACS impedance and the path impedance is less than the first ACS impedance and the path impedance is less than the second ACS impedance.

16. The ACC MOSFET according to claim 15, wherein the first ACS region couples to the floating body at a first ACS impedance and the second ACS couples to the floating body at a second ACS region impedance and the path impedance is greater than the first ACS impedance and the path impedance is greater than the second ACS impedance.

17. The ACC MOSFET according to claim 13, wherein the ACC MOSFET has an operational body to gate bias voltage and the first ACS region and the second ACS region have a parasitic MOS capacitance turned on at a voltage threshold and wherein the first ACS region and the second ACS region are doped with selected dopant materials and at selected dopant levels to provide that the parasitic MOS capacitance is turned on at a voltage threshold less than or greater than the desired operational body to gate bias voltage.

18. The ACC MOSFET according to claim 17, wherein the floating body comprises material doped with a first dopant and the first ACS region and the second ACS region comprise material doped with a second dopant, wherein the second dopant is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

19. The ACC MOSFET according to claim 17, wherein the floating body comprises material doped with a dopant at a first doping level and the first ACS region and the second ACS region comprise material doped with the dopant at a second doping level, wherein the second doping level is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

20. The ACC MOSFET according to claim 17, wherein the floating body comprises material doped with a first dopant at a first doping level and the first ACS region and the second ACS region comprise material doped with a second dopant at a second doping level, wherein the second dopant and second doping level are selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

21. The ACC MOSFET according to claim 13, wherein the first ACS region and first electrical contact region are coextensive and the second ACS region and second electrical contact region are coextensive.

22. The ACC MOSFET according to claim 13, wherein the first electrical contact region and first ACS region comprise the same material and the second electrical contact region and second ACS region comprise the same material.

23. The ACC MOSFET according to claim 13, wherein the first electrical contact region and first ACS region comprise different material and second electrical contact region and second ACS region comprise different material.

24. The ACC MOSFET according to claim 23, wherein the first electrical contact region and second electrical contact comprise an interconnection layer.

25. The ACC MOSFET according to claim 13, wherein the first ACS region and the second ACS region are electrically coupled to the gate.

26. The ACC MOSFET according to claim 13, wherein the ACC MOSFET comprises an ACC NMOSFET and wherein the source and drain comprise N+ doped regions, the floating body, first ACS region, and second ACS region comprise P−

doped regions, and the first electrical contact region and second electrical contact region comprise P+ doped regions.

27. The ACC MOSFET according to claim 26, wherein the first ACS region and the first electrical contact region are coextensive and the second ACS region and the second electrical contact region are coextensive and wherein the floating body, the first ACS region, and the second ACS region comprise a combined P−

doped region fabricated in a single ion-implementation manufacturing step.

28. The ACC MOSFET according to claim 13, wherein the drain, gate, first ACS region, and second ACS region are disposed symmetrically about a line defined by the middle of the floating body between the source and the drain.

29. An accumulated charge control floating body MOSFET (ACC MOSFET) adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising:

a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is operated in a non-conducting or near non-conducting state and charge accumulates within the body in a region proximate and underneath the gate oxide layer;

b) a plurality of accumulated charge sink regions positioned proximate portions of the floating body, wherein the plurality of accumulated charge sink regions comprise three or more accumulated charge sink regions, wherein the three or more accumulated charge sink regions are disposed symmetrically in relation to each other and to the floating body, and wherein each accumulated charge sink of the plurality of accumulated charge sink regions is electrically coupled to the floating body, and wherein, when the MOSFET is operated in the accumulated charge regime, ACS bias voltages are applied to each accumulated charge sink region to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the plurality of accumulated charge sink regions; and

c) a plurality of electrical contact regions positioned proximate to corresponding accumulated charge sink regions, wherein each electrical contact region facilitates electrical coupling to the corresponding accumulated charge sink region.

30. The ACC MOSFET according to claim 29, wherein the ACC MOSFET has an operational body to gate bias voltage and the plurality of accumulated charge sink regions have a parasitic MOS capacitance turned on at a voltage threshold and wherein the plurality of accumulated charge sink regions are doped with selected dopant materials and at selected dopant levels to provide that the parasitic MOS capacitance is turned on at a voltage threshold less than or greater than the operational body to gate bias voltage.

31. The ACC MOSFET according to claim 30, wherein the floating body comprises material doped with a first dopant and the plurality of accumulated charge sinks comprise material doped with a second dopant, wherein the second dopant is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

32. The ACC MOSFET according to claim 30, wherein the floating body comprises material doped with a dopant at a first doping level and the plurality of accumulated charge sinks comprise material doped with the dopant at a second doping level, wherein the second doping level is selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

33. The ACC MOSFET according to claim 30, wherein the floating body comprises material doped with a first dopant at a first doping level and the plurality of accumulated charge sinks comprise material doped with a second dopant at a second doping level, wherein the second dopant and second doping level are selected to turn on the parasitic MOS capacitance at a voltage threshold less than or greater than the operational body to gate bias voltage.

34. The ACC MOSFET according to claim 29, wherein the plurality of electrical contact regions are in electrical contact with one another and wherein the electrical contact among the electrical contact regions is provided by one or more paths having one or more path impedances.

35. The ACC MOSFET according to claim 34, wherein each accumulated charge sink region couples to the floating body at one or more accumulated charge sink impedances and the one or more path impedances are less than the one or more accumulated charge sink impedances.

36. The ACC MOSFET according to claim 34, wherein each accumulated charge sink region couples to the floating body at one or more accumulated charge sink impedances and the one or more path impedances are greater than the one or more accumulated charge sink impedances.

37. The ACC MOSFET according to claim 29, wherein each accumulated charge sink region is coextensive with its corresponding electrical contact region.

38. The ACC MOSFET according to claim 29, wherein each accumulated charge sink region and its corresponding electrical contact region comprise the same material.

39. The ACC MOSFET according to claim 29, wherein each accumulated charge sink region and its corresponding electrical contact region comprise different material.

40. The ACC MOSFET according to claim 39, wherein the plurality of electrical contact regions comprise an interconnection layer.

41. The ACC MOSFET according to claim 29, wherein each electrical contact region is independently connected to the gate.

42. The ACC MOSFET according to claim 29, wherein the plurality of accumulated charge sink regions are symmetrically two-dimensionally disposed in relation to the floating body and to each other.

43. The ACC MOSFET according to claim 29, wherein the plurality of accumulated charge sink regions are symmetrically three-dimensionally disposed in relation to the floating body and to each other.

44. The ACC MOSFET according to claim 29, further comprising a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and one or more ACS terminals electrically coupled to one or more of the electrical contact regions.

45. The ACC MOSFET according to claim 44, wherein the one or more ACS terminals are coupled to an accumulated charge sinking mechanism.

46. The ACC MOSFET according to claim 29, wherein the plurality of accumulated charge sink regions are located proximate the gate oxide layer.

47. The ACC MOSFET according to claim 29, wherein the drain, gate, are plurality of accumulated charge sink regions are disposed symmetrically about a line defined by the middle of the floating body between the source and the drain.