Self-aligned process for fabricating voltage-gated MRAM

• US 9,087,983 B2
• Filed: 02/25/2014
• Issued: 07/21/2015
• Est. Priority Date: 02/25/2013
• Status: Active Grant

• Current Assignee: Yimin Guo
• Original Assignee: Yimin Guo
• Inventors: Guo, Yimin
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US14/188,699
• Publication Number:
  US 20140241047A1
• Time in Patent Office: 511 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/209, 365/213, 365/225.5, 365/230.07, 365/232, 365/243.5, 257/421, 257/E21.665, 438/3, 977933-935
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. A bit line is coupled to the memory element through an upper electrode provided on the top surface of a reference layer, a select CMOS is coupled to the recording layer of the memory element through a middle second electrode and a VIA and a digital line is coupled to a voltage gate which is insulated from the recording layer by a dielectric layer and is used to adjust the switching write current. The fabrication includes formation of bottom digital line, formation of memory cell & VIA connection, formation of top bit line. Dual photolithography patterning and hard mask etch are used to form a small memory pillar. Ion implantation is used to convert a buried dielectric VIA into an electrical conducting path between middle memory cell and underneath CMOS device.

Claims

1. A spin-transfer torque magnetoresistive memory comprising a control circuitry and at least one memory cell comprising:

a digital line provided on a surface of a substrate serving as a bottom electrode;

a dielectric functional layer provided on the top surface of the digital line layer;

a recording layer provided on the top surface of the dielectric functional layer having a magnetic anisotropy and a variable magnetization direction and having an induced perpendicular anisotropy from a interface interaction with the functional layer;

a tunnel barrier layer provided on the top surface of the recording layer;

a reference layer provided on the top surface of the tunnel barrier having magnetic anisotropy and having a fixed magnetization direction;

a cap layer provided on the top surface of the reference layer as an upper electric electrode;

a middle electrode provided on sides of the recording layer and electrically connected to the recording layer;

a bit line provided on the top surface of the cap layer;

a select CMOS transistor coupled the middle electrode of magnetoresistive memory elements through a conductive VIA;

The control circuitry coupled through the bit line, the digital line and the select transistor to selected ones of the plurality of magnetoresistive memory elements,

The control circuitry further configured to provide a bi-directional spin-transfer recording current between the bit line and the select transistor and to provide a voltage on the digital line to generate an electric field on the dielectric functional layer to manipulate the induced perpendicular anisotropy in the recording layer in a recording operation,

The control circuitry further configured to provide a reading current between the bit line and the select transistor in a reading operation.

2. A method of manufacturing a magnetoresistive memory cell comprising

a digital line provided on a surface of a substrate serving as a bottom electrode;

a dielectric functional layer provided on the top surface of the digital line layer;

a recording layer provided on the top surface of the dielectric functional layer having a magnetic anisotropy and a variable magnetization direction and having a induced perpendicular anisotropy from a interface interaction with the functional layer;

a tunnel barrier layer provided on the top surface of the recording layer;

a reference layer provided on the top surface of the tunnel barrier having magnetic anisotropy and having a fixed magnetization direction;

a cap layer provided on the top surface of the reference layer as an upper electric electrode;

a conductive VIA electrically connected to a select CMOS transistor;

a middle electrode provided on sides of the recording layer and electrically connected to the recording layer and the VIA;

a bit line provided on the top surface of the cap layer;

and comprising a self-aligned patterning process to make the middle electrode electrically connected to the recording layer and the VIA;

and said recording layer is modulated by the voltage between said digital line and said middle electrode, which could be perpendicular to the plane or lie in the plane.

3. The element of claim 2, wherein the formation of said digital line begins with film stack deposition, photolithography patterning, RIE etch, dielectric refill and CMP to flatten the surface.

4. The element of claim 2, wherein said digital line comprises a film stack of Ta/X/Ta, or Ta/NiFe/X/NiFe(optional)/Ta with X being Ru, Cu, Ag, Al, Au, or an alloy of them, having a bottom Ta thickness between 1-3 nm and top Ta thickness between 10-40 nm, X thickness between 10-50 nm and NiFe thickness between 2-6 nm.

5. The element of claim 2, wherein a memory film stack consisting of said dielectric functional layer, said recording layer, said tunnel barrier layer, said reference layer, said cap layer and a hard mask layer is deposited on top of said digital line.

6. The element of claim 2, wherein said dielectric function layer, having a thickness between 1-3 nm, is a single layer Y made of metal oxide, or nitride, oxynitride, preferred to be selected from MgO, MgZnO, MgN, MgON, or a bi-layer Z/Y, Z is made of an oxide, or nitride, oxynitride, preferred to be AlOx or SiOx, having a thickness between 1-2 nm.

7. The element of claim 2, wherein said recording layer is a CoFeB layer having a thickness between 1-2 nm or a bi-layer CoFeB/CoFe having CoFe as an interface dusting layer having a thickness between 0.2-0.5 nm and immediately adjacent to said tunnel barrier layer.

8. The element of claim 2, wherein said reference layer is preferred to be CoFeB/TbCoFe, CoFeB/CoPt, CoFeB/CoPd, CoFeB/(Co/Pt)n, CoFeB/(Co/Pd)n having a thickness between 2-10 nm.

9. The element of claim 2, wherein said capping layer is preferred to be a Ru layer having a thickness between 1-2 nm, and said hard mask layer is preferred to be Ta, or Ta alloy having a thickness between 10-40 nm.

10. The element of claim 2, wherein said bit line has a film stack of Ta/X/Ta, or Ta/NiFe/X/NiFe(optional)/Ta with X being selected from Ru, Cu, Ag, Al, Au, or an alloy of them, having a bottom Ta thickness between 1-3 nm and top Ta thickness between 10-40 nm, X thickness between 40-80 nm and NiFe thickness between 2-10 nm.

11. The element of claim 2, further comprising a single or dual photo patterning and hard mask etching process to first create a Ta hard mask pillar array, and said hard mask etch comprising an RIE etch using a chemical gas CxFyHz, preferred to be CF4, CF3H, having an etch stop on Ru cap layer, and O2 or Ar/O2 ashing removal of the remaining photoresist and associated Ta re-dep.

12. The element of claim 2, further comprising a TMR etch process, preferred to be an RIE process using a mixed chemical gases CO and NH4 or a chemical gas CH3OH, C2H5OH, and stopping on the said tunnel barrier layer controlled by an end-point signal detection.

13. The element of claim 2, further comprising a conformal deposition of a thin dielectric layer on the etch-opened TMR junction, and the said thin dielectric covering layer is preferred to be made by atomic layer deposition (ALD) of a single AlOx layer, or a bi-layer of MgO/AlOx, SiN/AlOx, having an AlOx thickness of 4-8 nm, an MgO thickness of around 2 nm, a SiN thickness of around 2 nm.

14. The element of claim 2, further comprising a patterning process to open a VIA area on the conformal dielectric covering layer on device surface using a photoresist mask.

15. The element of claim 14, further comprising an ion implantation process conducted in the VIA areas using ion element is selected from Li, Cu, Al, Ag, Au, Ru, Pt with photoresist patterning acting as ion implantation mask.

16. The element of claim 14, further comprising a deep etch in the exposed VIA by ion mill to remove all the materials starting from top dielectric layer, MgO barrier layer, middle memory stack layer, and bottom dielectric function layer.

17. The element of claim 14, wherein said remaining photoresist is removed by O2 or Ar/O2 ashing after the ion implantation process or deep etching.

18. The element of claim 17, wherein a normal (perpendicular to the flat surface) sputter etching using low-angle ion milling to remove the dielectric covering layer and MgO barrier layer from the device surface.

19. The element of claim 18, further comprising a normal deposition of a conducting metal layer on the surface including the VIA open area by low-angle ion deposition or physical vapor deposition.

20. The element of claim 19, further comprising a normal deposition of a thin dielectric layer to cover the said conducting metal layer.

21. The element of claim 20, further comprising a glazing (large) angle ion mill to move the said metal layer near the vertical MTJ junction wall.

22. The element of claim 21, further comprising a photolithography patterning and etch process to create a conductive path between said TMR memory cell and said VIA.

23. The element of claim 22, further comprising a deposition of a thick dielectric layer, preferred to be SiN or SiOx, to cover the entire device surface, followed a CMP process to flatten the device surface and stop on Ta hard mask pillar.

24. The element of claim 2, wherein said bit line film stack is deposited to electrically contact to said Ta hard mask layer, and said bit line is photolighography patterned and etch by RIE.

25. The element of claim 24, wherein the etched bit line is refilled by a thick (100 nm) dielectric layer of SiO2 or SiN/SiOx, and the refilled surface is flattened by CMP using Ta as the stopping layer.

26. The element of claim 2 is further annealed at certain high temperature to repair the ion implantation damage and to release the process induced stress.

27. The element of claim 2, wherein the as-formed three-terminal memory has its current path flow between said bit line and VIA to the underneath select CMOS transistor and a voltage controlled gate between said middle electrode and said digital line.