Scan chain masking qualification circuit shift register and bit-field decoders
First Claim
1. Electronic scan circuitry comprising:
- a decompressor;
a plurality of scan chains fed by the decompressor;
a scan circuit coupled to the plurality of scan chains to scan them in and out;
a masking circuit fed by the scan chains;
a scannable masking qualification circuit coupled to the masking circuit, the masking qualification circuit scannable by scan-in of bits by the decompressor along with scan-in of the scan chains, and the scannable masking qualification circuit operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit, the scannable masking qualification circuit having a shift register fed by the decompressor that includes sets of shift register cells; and
bit-field decoders, each set of shift register cells coupling a bit-field to a corresponding one of the bit-field decoders, each one such decoder having a decode output coupled to the masking circuit to independently select at least one scan chain for qualification in a distinct respective group among the scan chains for each one such decoder corresponding to each such set of shift register cells in the shift register.
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Accused Products
Abstract
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.
39 Citations
2 Claims
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1. Electronic scan circuitry comprising:
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a decompressor; a plurality of scan chains fed by the decompressor; a scan circuit coupled to the plurality of scan chains to scan them in and out; a masking circuit fed by the scan chains; a scannable masking qualification circuit coupled to the masking circuit, the masking qualification circuit scannable by scan-in of bits by the decompressor along with scan-in of the scan chains, and the scannable masking qualification circuit operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit, the scannable masking qualification circuit having a shift register fed by the decompressor that includes sets of shift register cells; and bit-field decoders, each set of shift register cells coupling a bit-field to a corresponding one of the bit-field decoders, each one such decoder having a decode output coupled to the masking circuit to independently select at least one scan chain for qualification in a distinct respective group among the scan chains for each one such decoder corresponding to each such set of shift register cells in the shift register. - View Dependent Claims (2)
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Specification