Systems and methods of performing a data save operation

• US 9,092,150 B2
• Filed: 12/22/2011
• Issued: 07/28/2015
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Yerushalmi, Daniel Zvi, Iarovici, Yaniv
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): RUSSELL, ANDREW D
• Application Number:
  US13/335,180
• Publication Number:
  US 20130166864A1
• Time in Patent Office: 1,314 Days
• Field of Search: 711/162, 713/323
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3221 of disk drive devices
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method includes determining, based on an indication from a host device operatively coupled to a data storage device that includes a controller, a non-volatile memory including a hibernate area, a volatile memory, a non-volatile memory interface, and a volatile memory interface, that the data storage device is to enter a low-power state. The method includes, in response to determining that the data storage device is to enter a low-power state, performing a data save operation. The data save operation bypasses the non-volatile memory interface and the volatile memory interface and copies data from the volatile memory of the data storage device to the hibernate area of the non-volatile memory of the data storage device.

Claims

1. A method comprising:

in a data storage device with a controller, a volatile memory, a non-volatile memory including a hibernate data area, and a hibernate data bus, the hibernate data area interfaced with the volatile memory via the hibernate data bus, wherein the data storage device further includes a non-volatile memory interface to enable access to the non-volatile memory by a host device and a volatile memory interface to enable access to the volatile memory by the host device, performing by the controller;

determining, based on an indication from the host device, that the data storage device is to enter a low-power state; and

in response to determining that the data storage device is to enter the low-power state, performing a data save operation by generating a first control signal to cause transfer of data from the volatile memory to the hibernate data bus and by generating a second control signal to cause transfer of the data from the hibernate data bus to the hibernate data area of the non-volatile memory.

2. The method of claim 1, wherein performing the data save operation prevents loss of the data upon interruption of power to the volatile memory.

3. The method of claim 1, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a power event signal from the host device, wherein the power event signal is a hardware signal indicating a sleep state or a power off state.

4. The method of claim 3, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation, wherein entering the hibernation state is performed without host device intervention.

5. The method of claim 1, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a hibernation instruction from an application processor of the host device.

6. The method of claim 1, wherein the controller is configured to detect that a timer value exceeds a hibernation threshold, wherein the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory.

7. The method of claim 6, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation.

8. The method of claim 7, wherein entering the hibernation state is performed without host device action.

9. The method of claim 1, wherein the controller is further configured, upon completion of the data save operation, to power off the volatile memory while a power control circuit maintains power to the controller.

10. The method of claim 1, wherein the controller is further configured, upon completion of the data save operation, to provide an indication to the host device that the data storage device is prepared for interruption of power.

11. The method of claim 1, wherein the controller is coupled to the non-volatile memory via a bus.

12. The method of claim 11, wherein the controller is configured to perform a data restore operation that includes copying stored data from the non-volatile memory to the volatile memory.

13. The method of claim 1, wherein the controller is configured to perform a data restore operation that includes copying stored data from the non-volatile memory to the volatile memory to restore a memory image of the volatile memory.

14. The method of claim 1, wherein performing the data save operation includes selectively copying portions of the volatile memory to the non-volatile memory based on whether the portions have been modified since a most recent data restore operation.

15. A data storage device comprising:

a non-volatile memory, wherein the non-volatile memory includes a hibernate data area;

a volatile memory;

a non-volatile memory interface to the non-volatile memory configured to allow access to the non-volatile memory by a host device;

a volatile memory interface to the volatile memory configured to allow access to the volatile memory by the host device;

a hibernate data bus configured to interface the hibernate data area with the volatile memory; and

a controller configured to generate a first control signal to cause transfer of data from the volatile memory to the hibernate data bus and to generate a second control signal to cause transfer of the data from the hibernate data bus to the hibernate data area of the non-volatile memory, and to perform a data save operation in response to determining, based on an indication from the host device, that the data storage device is to enter a low-power state.

16. The data storage device of claim 15, wherein performing the data save operation prevents loss of the data upon interruption of power to the volatile memory.

17. The data storage device of claim 15, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a power event signal from the host device, wherein the power event signal is a hardware signal indicating a sleep state or a power off state.

18. The data storage device of claim 17, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation, wherein entering the hibernation state is performed without host device intervention.

19. The data storage device of claim 15, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a hibernation instruction from an application processor of the host device.

20. The data storage device of claim 15, wherein the controller is configured to detect that a timer value exceeds a hibernation threshold, wherein the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory.

21. The data storage device of claim 20, wherein the controller is configured to determine that the data storage device is to enter a hibernation state after performing the data save operation.

22. The data storage device of claim 21, wherein entering the hibernation state is performed without host device action.

23. The data storage device of claim 15, wherein the controller is further configured, upon completion of the data save operation, to power off the volatile memory.

24. The data storage device of claim 15, wherein the controller is further configured, upon completion of the data save operation, to provide an indication to the host device that the data storage device is prepared for interruption of power.

25. The data storage device of claim 15, wherein the controller is coupled to the non-volatile memory via a bus.

26. The data storage device of claim 25, wherein the controller is configured to perform a data restore operation that includes copying stored data from the non-volatile memory to the volatile memory.

27. The data storage device of claim 15, wherein the controller is configured to perform a data restore operation that includes copying stored data from the non-volatile memory to the volatile memory to restore a memory image of the volatile memory.

28. The data storage device of claim 15, wherein performing the data save operation includes selectively copying portions of the volatile memory to the non-volatile memory based on whether the portions have been modified since a most recent data restore operation.

29. A method comprising:

in a data storage device with a controller, a non-volatile memory, a volatile memory, and a hibernate data bus, wherein the hibernate data bus enables a data transfer from the volatile memory to the non-volatile memory that bypasses the controller;

determining, based on an indication from a host device, that the data storage device is to enter a low-power state; and

in response to determining that the data storage device is to enter the low-power state, performing a data save operation by directly copying data from the volatile memory to the non-volatile memory via the hibernate data bus.

30. The method of claim 29, wherein the data storage device includes a non-volatile memory interface to enable access to the non-volatile memory by the host device, wherein the data storage device includes a volatile memory interface to enable access to the volatile memory by the host device.

31. The method of claim 29, further comprising, upon completion of the data save operation, powering off the volatile memory while maintaining power to the controller.

32. The method of claim 29, further comprising, upon completion of the data save operation, sending an indication to the host device that the data storage device is prepared for interruption of power.

33. The method of claim 29, wherein the non-volatile memory includes a hibernate area, wherein the controller is coupled to the hibernate data bus, wherein the hibernate data bus connects the non-volatile memory and the volatile memory, and wherein performing the data save operation includes:

generating a first bus control signal to cause the hibernate data bus to access the data from the volatile memory; and

generating a second bus control signal to cause the hibernate data bus to send the data to the hibernate area of the non-volatile memory.

34. A data storage device comprising:

a non-volatile memory;

a volatile memory;

a controller;

a hibernate data bus that connects the non-volatile memory and the volatile memory, wherein the hibernate data bus enables a data transfer from the volatile memory to the non-volatile memory that bypasses the controller; and

wherein the controller is configured to perform a data save operation by directly copying data from the volatile memory to the non-volatile memory via the hibernate data bus in response to determining, based on an indication from a host device, that the data storage device is to enter a low-power state.

35. The data storage device of claim 34, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a power event signal from the host device, wherein the power event signal is a hardware signal indicating a sleep state or a power off state.

36. The data storage device of claim 34, wherein the controller is configured to determine that the data storage device is to enter the low-power state by detecting receipt of a hibernation instruction from an application processor of the host device.

37. The data storage device of claim 34, wherein the controller is configured to detect that a timer value exceeds a hibernation threshold, wherein the timer value indicates an elapsed time since receipt of a request from the host device to access the volatile memory.