Microprocessor unit capable of multiple power modes having a register with direct control bits and register pointer bits for indirect control

• US 9,092,206 B2
• Filed: 05/03/2010
• Issued: 07/28/2015
• Est. Priority Date: 05/04/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rzehak, Volker, Diewald, Horst
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Chan, Danny
• Application Number:
  US12/772,442
• Publication Number:
  US 20140047247A1
• Time in Patent Office: 1,912 Days
• Field of Search: 713/300
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power mode control system for microprocessors offers an unlimited variety of hardware-supported power modes that may satisfy any operating scenario. The microprocessor unit comprises a register that contains particular bit fields for defining selectable power modes. The particular bit fields in the register define pointers to a power mode defining register. Each pointer selects a corresponding bit field in the power mode defining register. The bits in the bit fields of the power mode defining register either directly control a power mode of at least one functional or peripheral blocks of the unit; or they are pointers to a further power mode defining register and the bits in the bit fields of the further power mode defining register directly control a power mode of at least one functional or peripheral blocks of the unit.

Claims

1. A microprocessor unit capable of multiple power modes, comprising:

at least one register containing a bit field including less than all bits of said at least one register, said bit field having a plurality of bit field encodings, wherein

a first set of said plurality of bit field encodings directly controls at least one of said power modes, and

a second set of said plurality of bit field encodings define pointers to at least one power mode defining register.

2. The microprocessor unit according to claim 1, wherein:

at least some of said first set of said plurality of bit field encodings in the register directly controls a power mode of at least one functional block of the microprocessor unit.

3. The microprocessor unit according to claim 1, wherein:

the bits in the bit fields of the power mode defining register directly control a power mode of at least one functional block of the microprocessor unit.

4. The microprocessor unit according claim 1, wherein:

the bits in the bit fields of the power mode defining register are pointers to a further power mode defining register and the bits in bit fields of the further power mode defining register directly control a power mode of at least one functional block of the microprocessor unit.

5. The microprocessor unit according claim 1, wherein:

said register holding said bit field is an existing register of the unit such as a status register, a CPU register and a memory area.

6. The micrFoprocessor unit according claim 1, wherein:

said register holding said bit field is responsive to control events.