Detection and handling of unbalanced errors in interleaved codewords

• US 9,092,350 B1
• Filed: 09/11/2013
• Issued: 07/28/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Jeon, Seungjune, Chen, Xiaoheng
• Primary Examiner(s): Trimmings, John P
• Application Number:
  US14/024,531
• Time in Patent Office: 685 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H01L 2924/1438 Flash memory
• CPC Class Codes: H01L 2924/1443 Non-volatile random-access memory [NVRAM]
• CPC Class Codes: H03M 13/3723 using means or methods for the initialisation of the decoder
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation

Abstract

Mechanisms are provided for detecting whether at least one of two or more portions of memory (e.g. chips, blocks, sectors, planes, pages, word lines, etc.) are more error-prone than the others, when portions of codewords are interleaved across the two or more portions of memory. Some implementations also enable various remedial operations that can be selectively employed in response to detecting an unbalanced error condition in order to reduce the risks associated with interleaving portions of codewords across two or more portions of memory.

Claims

1. A method of estimating error propensities of two or more portions of memory, wherein the two or more portions of memory are each used to store respective portions of each codeword in a set of codewords, the method comprising:

reading data from memory comprising one or more codewords in the set of codewords, each codeword of the one or more codewords read from memory including two or more portions that are each read from a distinct portion of the two or more portions of memory; and

computing two or more error propensity metrics, each error propensity metric corresponding to a respective portion of memory, wherein each error propensity metric is computed using a corresponding sub-matrix of a parity check matrix associated with the set of codewords and the respective portions of the one or more codewords read from the corresponding portion of memory.

2. The method of claim 1, further comprising:

determining whether a respective error propensity metric, of the two or more error propensity metrics, satisfies remedial correction criteria, the remedial correction criteria including a criterion that the respective error propensity metric is outside a threshold range; and

in response to determining that the respective error propensity metric is outside the threshold range, performing a remedial operation on the portion of memory corresponding to the respective error propensity metric that has been determined to be outside the threshold range.

3. The method of claim 1, further comprising:

identifying a respective error propensity metric, of the two or more error propensity metrics, that satisfies remedial correction criteria, the remedial correction criteria including a criterion that the identified respective error propensity metric is outside a range associated with one or more other error propensity metrics of the two or more error propensity metrics; and

in response to identifying the respective error propensity metric, performing a remedial operation on the portion of memory corresponding to the identified respective error propensity metric.

4. The method of claim 2, wherein the remedial operation comprises adjusting a reading signal level used to read the corresponding one of the two or more portions of memory.

5. The method of claim 4, wherein the reading signal level includes a reading threshold voltage.

6. The method of claim 2, wherein the remedial operation comprises:

performing one or more additional read operations of the corresponding one of the two or more portions of memory using one or more reading signal levels; and

producing a soft information value using the results of the one or more additional read operations.

7. The method of claim 2, wherein the remedial operation comprises selecting soft information values from a characterization vector based on one or more characterization parameter values associated with a current state of the corresponding one of the two or more portions of memory.

8. The method of claim 7, wherein the remedial operation further comprises adjusting the selected soft information values based on the error propensity metric identified as outside the threshold range.

9. The method of claim 1, wherein each of the two or more sub-matrices comprises a sub-optimal parity check matrix within the parity check matrix associated with the whole codeword.

10. The method of claim 1, wherein computing the two or more error propensity metrics comprises computing two or more sub-syndrome matrices, wherein each sub-syndrome matrix is a function of a corresponding one of the two or more portions of the codeword and a corresponding one of the two or more sub-matrices.

11. The method of claim 10, wherein computing the two or more error propensity metrics comprises computing two or more probability values, wherein each probability value is representative of a likelihood that an element of a corresponding one of the two or more sub-syndrome matrices has a first predefined value.

12. The method of claim 11, wherein each probability value is a function of a dividend value indicative of a summation of elements, in a corresponding one of the two or more sub-syndrome matrices, that have a first predefined value, and a divisor value corresponding to the number of rows in a corresponding one of the two or more first sub-matrices.

13. The method of claim 11, wherein computing the two or more error propensity metrics comprises computing two or more bit error rate values, wherein each bit error rate value is a function of a corresponding one of the two or more probability values and a respective syndrome weight associated with a corresponding one of the two or more first sub-matrices.

14. The method of claim 10, wherein computing the two or more error propensity metrics comprises retrieving two or more bit error rate ranges, wherein each bit error rate range is associated with a corresponding one of the two or more sub-syndrome matrices.

15. The method of claim 14, wherein retrieving the two or more bit error rate ranges includes selecting from a characterization vector based on one or more characterization parameter values associated with a current state of the corresponding one of the two or more portions of memory.

16. The method of claim 1, wherein the codeword is a low density parity check (LDPC) codeword.

17. The method of claim 1, wherein the two or more portions of memory are substantially independent from one another.

18. The method of claim 1, wherein each of the two or more portions of memory includes at least one of a memory die having an array of memory cells, a block of memory cells, a plane of memory cells, a word line of memory cells.

19. A non-transitory computer readable medium including instructions for estimating error propensities of two or more portions of memory, wherein the two or more portions of memory are each used by to store respective portions of each codeword in a set of codewords, the instructions when executed by a processor cause a device to:

read data from memory comprising one or more codewords in the set of codewords, each codeword of the one or more codewords read from memory including two or more portions that are each read from a distinct portion of the two or more portions of memory; and

compute two or more error propensity metrics, each error propensity metric corresponding to a respective portion of memory, wherein each error propensity metric is computed using a corresponding sub-matrix of a parity check matrix associated with the set of codewords and the respective portions of the one or more codewords read from the corresponding portion of memory.

20. A memory controller configured to estimating error propensities of two or more portions of memory, wherein the two or more portions of memory are each used to store respective portions of each codeword in a set of codewords, the memory controller comprising:

a storage medium interface configured to read data from memory comprising one or more codewords in the set of codewords, each codeword of the one or more codewords read from memory including two or more portions that are each read from a distinct portion of the two or more portions of memory; and

a sub-matrix error detection module configured to identify whether one of the two or more portions of memory has a relatively higher error propensity than the others by determining a corresponding error propensity metric for each of the two or more portions of memory based on a corresponding sub-matrix of a parity check matrix associated with the set of codewords and the respective portions of the one or more codewords read from the corresponding portion of memory.

21. The memory controller of claim 20, wherein the sub-matrix error detection module comprises:

an error propensity metric calculator configured to compute the two or more error propensity metrics, each error propensity metric corresponding to a respective portion of memory, wherein each error propensity metric is computed using the corresponding sub-matrix of the parity check matrix associated with the set of codewords and the respective portions of the one or more codewords read from the corresponding portion of memory.

22. The memory controller of claim 20, wherein the sub-matrix error detection module comprises:

a comparator configured to determine whether a respective error propensity metric, of the two or more error propensity metrics, satisfies remedial correction criteria, the remedial correction criteria including a criterion that the respective error propensity metric is outside a threshold range.

23. The memory controller of claim 20, wherein the sub-matrix error detection module comprises:

a comparator configured to identify a respective error propensity metric, of the two or more error propensity metrics, that satisfies remedial correction criteria, the remedial correction criteria including a criterion that the identified respective error propensity metric is outside a range associated with one or more other error propensity metrics of the two or more error propensity metrics.

24. The memory controller of claim 20, wherein the sub-matrix error detection module comprises:

a remedial read module configured to perform a remedial operation on the portion of memory having a relatively higher error propensity than the others based on the determined error propensity metrics.

25. The memory controller of claim 24, wherein the remedial operation comprises adjusting a reading signal level used to read the corresponding one of the two or more portions of memory.

26. The memory controller of claim 25, wherein the reading signal level includes a reading threshold voltage.

27. The memory controller of claim 25, wherein the remedial operation comprises:

performing one or more additional read operations of the corresponding one of the two or more portions of memory using one or more reading signal levels; and

producing a soft information value using the results of the one or more additional read operations.

28. The memory controller of claim 25, wherein the remedial operation comprises selecting soft information values from a characterization vector based on one or more characterization parameter values associated with a current state of the corresponding one of the two or more portions of memory.

29. The memory controller of claim 25, wherein the remedial operation further comprises adjusting the selected soft information values based on the error propensity metric identified as outside the threshold range.

30. The memory controller of claim 20, wherein computing the two or more error propensity metrics comprises computing two or more sub-syndrome matrices, wherein each sub-syndrome matrix is a function of a corresponding one of the two or more portions of the codeword and a corresponding one of the two or more sub-matrices, and computing two or more probability values, wherein each probability value is representative of a likelihood that an element of a corresponding one of the two or more sub-syndrome matrices has a first predefined value.