Discrete three-dimensional memory comprising dice with different BEOL structures

• US 9,093,129 B2
• Filed: 10/06/2013
• Issued: 07/28/2015
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US14/047,011
• Publication Number:
  US 20140036566A1
• Time in Patent Office: 660 Days
• Field of Search: 257/296, 257/303, 257/311, 257/314, 257/315, 257/686, 438/238, 438/241, 438/257, 438/258, 438/262, 438/264, 438/266
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group

Abstract

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-M is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures, e.g. different number of BEOL layers, different number of interconnect layers, and/or different interconnect materials.

Claims

1. A discrete three-dimensional memory (3DM), comprising:

a 3D-array die comprising a plurality of 3D-M arrays, each of said 3D-M arrays including a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least a peripheral-circuit component for said 3D-M array;

means for coupling said 3D-array die and said peripheral-circuit die;

wherein said peripheral-circuit component is absent from said 3D-array die;

said 3D-array die comprises more back-end-of-line (BEOL) layers than said peripheral-circuit die; and

, said 3D-array die and said peripheral-circuit die are separate dice.

2. The memory according to claim 1, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

3. The memory according to claim 1, wherein said 3D-M comprises at least one of 3D-memristor, 3D-RRAM or 3D-ReRAM (resistive random-access memory), 3D-PCM (phase-change memory), 3D-PMC (programmable metallization-cell memory), and 3D-CBRAM (conductive-bridging random-access memory).

4. The memory according to claim 1, wherein said peripheral-circuit component is selected from a group of peripheral-circuit components consisting of read-voltage generator, write-voltage generator, address translator and data translator.

5. The memory according to claim 1, wherein said peripheral-circuit component is selected from a group of peripheral-circuit components consisting of band-gap reference generator, VR generator, charge-pump circuit, boost converter, low-dropout regulator, buck converter, oscillator, error checking and correction circuit, page register, fault memory, trim-bit circuit and smart write controller.

6. The memory according to claim 1, wherein said peripheral-circuit die further comprises at least a serializer-deserializer circuit.

7. The memory according to claim 1, wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.

8. The memory according to claim 1, further comprising another 3D-array die including at least another 3D-M array, wherein said peripheral-circuit die comprises at least another peripheral-circuit component for said another 3D-M array.

9. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising a plurality of 3D-M arrays, each of said 3D-M arrays including a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least a peripheral-circuit component for said 3D-M array;

means for coupling said 3D-array die and said peripheral-circuit die;

wherein said peripheral-circuit component is absent from said 3D-array die;

said peripheral-circuit die comprises at least one different interconnect material than said 3D-array die; and

, said 3D-array die and said peripheral-circuit die are separate dice.

10. The memory according to claim 9, wherein the interconnect materials of said 3D-array die are stable at a higher processing temperature than the interconnect materials of said peripheral-circuit die.

11. The memory according to claim 9, wherein at least an interconnect material of said peripheral-circuit die has a higher electrical conductivity than at least another interconnect material of said 3D-array die.

12. The memory according to claim 9, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

13. The memory according to claim 9, wherein said peripheral-circuit component is selected from a group of peripheral-circuit components consisting of read-voltage generator, write-voltage generator, address translator and data translator.

14. The memory according to claim 9, wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.

15. The memory according to claim 9, further comprising another 3D-array die including at least another 3D-M array, wherein said peripheral-circuit die comprises at least another peripheral-circuit component for said another 3D-M array.

16. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising a plurality of 3D-M arrays, each of said 3D-M arrays including a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least a peripheral-circuit component for said 3D-M array;

means for coupling said 3D-array die and said peripheral-circuit die;

wherein said peripheral-circuit component is absent from said 3D-array die;

said peripheral-circuit die comprises more interconnect layers than said 3D-array die; and

, said 3D-array die and said peripheral-circuit die are separate dice.

17. The memory according to claim 16, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

18. The memory according to claim 16, wherein said peripheral-circuit component is selected from a group of peripheral-circuit components consisting of read-voltage generator, write-voltage generator, address translator and data translator.

19. The memory according to claim 16, wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card or a solid-state drive.

20. The memory according to claim 16, further comprising another 3D-array die including at least another 3D-M array, wherein said peripheral-circuit die comprises at least another peripheral-circuit component for said another 3D-M array.