Methods and systems for staggered memory operations

• US 9,093,160 B1
• Filed: 06/06/2014
• Issued: 07/28/2015
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Ellis, Robert W., Higgins, James M., Mohan, Vidyabhushan
• Primary Examiner(s): Norman, James G
• Application Number:
  US14/298,843
• Time in Patent Office: 417 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The embodiments described herein are used to execute staggered memory operations. The method includes, at each of a plurality of distinct memory portions of the storage device, establishing a non-zero command delay parameter distinct from a command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions. The method further includes, after establishing the non-zero command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the command delay parameter established for that memory portion.

Claims

1. A method of operation in a storage device, comprising:

during operation of the storage device;

for each of a plurality of distinct memory portions of the storage device, establishing a non-zero value of a command delay parameter, wherein the non-zero value of the command delay parameter is distinct from a value of the command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions;

after establishing the non-zero value of the command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the non-zero value of the command delay parameter established for that memory portion.

2. The method of claim 1, wherein the plurality of memory portions comprise non-volatile memory portions.

3. The method of claim 1, wherein the plurality of memory portions comprise NAND flash memory portions.

4. The method of claim 1, wherein the storage device comprises one or more flash memory devices.

5. The method of claim 1, wherein the executed memory operations, executed in the two or more of the plurality of distinct memory portions of the storage device, include a plurality of operations of a same memory operation type, wherein the same memory operation type is selected from the group consisting of write operations, read operations and erase operations.

6. The method of claim 5, wherein the command delay parameter for each of the two or more of the plurality of distinct memory portions of the storage device is selected from the group consisting of a write delay parameter for controlling delay of write operations, a read delay parameter for controlling delay of read operations and an erase delay parameter for controlling delay of erase operations.

7. The method of claim 6, wherein the non-zero value of the command delay parameter for each of the two or more of the plurality of distinct memory portions of the storage device is less than or equal to an average duration of time for its corresponding memory operation.

8. The method of claim 1, including, while executing a sequence of memory operations in a single memory portion of the plurality of distinct memory portions of the storage device, delaying a first memory operation of the sequence of memory operations in accordance with the non-zero value of the command delay parameter established for that single memory portion, and thereafter executing each subsequent memory operation in the sequence of memory operations in sequential order without further delaying each said subsequent memory operation in the sequence of memory operations.

9. The method of claim 8, including detecting presence of the sequence of memory operations in a work queue associated with the single memory portion.

10. The method of claim 1, further comprising:

while executing memory write operations in a work queue associated with a first subset of the plurality of distinct memory portions of the storage device, executing a first subset of the memory write operations in the work queue in parallel with execution delayed by the amount of time corresponding to the non-zero value of the command delay parameter established for each memory portion to which write data is written by the first subset of the memory write operations in the work queue, and

thereafter executing each subsequent memory write operation in the work queue without further delaying each said subsequent memory write operation.

11. The method of claim 1, wherein one or more of the command delay parameters is stored in non-volatile memory.

12. The method of claim 1, further comprising, in an additional memory portion of the storage device, distinct from said plurality of memory portions of the storage device, executing memory operations during the overlapping time periods, without delaying execution of said memory operations in the additional memory portion of the storage device.

13. The method of claim 1, further comprising at an additional memory portion of the storage device, distinct from said plurality of memory portions of the storage device, establishing a zero value for a command delay parameter distinct from the command delay parameters established for said plurality of distinct memory portions, and executing memory operations in the additional memory portion of the storage device during the overlapping time periods in accordance with the zero value for the command delay parameter.

14. The method of claim 1, further comprising, for each of the plurality of distinct memory portions of the storage device, establishing non-zero values for two or more command delay parameters distinct from command delay parameters established for one or more of the other memory portions in the plurality of distinct memory portions, wherein the two or more command delay parameters include at least a first command delay parameter for use when executing a first command type selected from the set consisting of read, write and erase commands and a second command delay parameter for use when executing a second command type distinct from the first command type and selected from the set consisting of read, write and erase commands.

15. The method of claim 1, further comprising:

after establishing the non-zero value of the command delay parameter in each of the plurality of distinct memory portions of the storage device, and after delaying execution of a respective memory operation in each of the plurality of distinct memory portions by an amount of time corresponding to the non-zero value of the command delay parameter established for that memory portion;

adjusting the non-zero value of the command delay parameter corresponding to a first distinct memory portion of the plurality of memory portions.

16. The method of claim 15, wherein adjusting the non-zero value of the command delay parameter corresponding to a first distinct memory portion of the plurality of memory portions comprises:

reducing the value of the command delay parameter corresponding to a first distinct memory portion of the plurality of memory portions, to zero.

17. The method of claim 15, wherein adjusting the non-zero value of the command delay parameter corresponding to a first distinct memory portion of the plurality of memory portions comprises:

changing the value of the command delay parameter corresponding to a first distinct memory portion of the plurality of memory portions, to a new non-zero value.

18. The method of claim 1, wherein the storage device comprises one or more three-dimensional (3D) memory devices and circuitry associated with operation of memory elements in the one or more 3D memory devices.

19. The method of claim 18, wherein the circuitry and one or more memory elements in a respective 3D memory device, of the one or more 3D memory devices, are on the same substrate.

20. The method of claim 1, further comprising adjusting the non-zero value of the command delay parameter in accordance with an age of the corresponding memory portion.

21. A storage device, comprising:

an interface for coupling the storage device to a host system;

non-volatile memory, including multiple distinct memory portions of the non-volatile memory; and

a set of one or more storage controllers, having one or more processors, the set of one or more storage controllers configured to;

during operation of the storage device;

for each of a plurality of distinct memory portions of the storage device, establishing a non-zero value of a command delay parameter, wherein the non-zero value of the command delay parameter is distinct from a value of the command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions;

after establishing the non-zero value of the command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the non-zero value of the command delay parameter established for that memory portion.

22. The storage device of claim 21, wherein the plurality of memory portions comprises NAND flash memory portions.

23. The storage device of claim 21, wherein the executed memory operations, executed in the two or more of the plurality of distinct memory portions of the storage device, include a plurality of operations of a same memory operation type, wherein the same memory operation type is selected from the group consisting of write operations, read operations and erase operations.

24. The storage device of claim 23, wherein the command delay parameter for each of the two or more of the plurality of distinct memory portions of the storage device is selected from the group consisting of a write delay parameter for controlling delay of write operations, a read delay parameter for controlling delay of read operations and an erase delay parameter for controlling delay of erase operations.

25. The storage device of claim 21, wherein the set of one or more storage controllers is configured to, for each of the plurality of distinct memory portions of the storage device, establish non-zero values for two or more command delay parameters distinct from command delay parameters established for one or more of the other memory portions in the plurality of distinct memory portions, wherein the two or more command delay parameters include at least a first command delay parameter for use when executing a first command type selected from the set consisting of read, write and erase commands and a second command delay parameter for use when executing a second command type distinct from the first command type and selected from the set consisting of read, write and erase commands.

26. A non-transitory computer readable storage medium, storing one or more programs for execution by one or more processors of a storage device, the one or more programs including instructions for:

during operation of the storage device;

for each of a plurality of distinct memory portions of the storage device, establishing a non-zero value of a command delay parameter, wherein the non-zero value of the command delay parameter is distinct from a value of the command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions;

after establishing the non-zero value of the command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the non-zero value of the command delay parameter established for that memory portion.