Transistor structure having a trench drain

• US 9,093,300 B2
• Filed: 03/04/2014
• Issued: 07/28/2015
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Estivation Properties LLC (Intellectual Ventures LLC)
• Inventors: Davies, Robert Bruce
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US14/196,063
• Publication Number:
  US 20140183623A1
• Time in Patent Office: 511 Days
• Field of Search: 257/328, 257/341, 257/E29.03, 438/524
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Claims

1. A device comprising:

a tub region of a transistor having a first depth, wherein the tub region includes at least a portion of a channel region of the transistor;

a first trench in a drain region of the transistor having a second depth greater than or equal to the first depth; and

a second trench formed within a surface of the first trench such that second trench is disposed below the first trench.

2. The device of claim 1, further comprising a first dopant of a same type as the drain region in proximity to a surface of the drain region and in proximity to the channel region of the transistor to support current flow out of the channel region and into the drain region.

3. The device of claim 2, further comprising a second dopant implanted through a sidewall of the first trench to support current flow in proximity to the first trench adjacent to the sidewall of the first trench.

4. The device of claim 1, wherein the second depth is greater than two times the first depth.

5. The device of claim 1, wherein the second trench forms a physical boundary for the drain region and is configured to provide a field line edge termination for the transistor.

6. The device of claim 1, further comprising a dielectric layer on a sidewall surface of the second trench.

7. The device of claim 1, further comprising a first conductive shield formed within the first trench and approximately parallel to a sidewall of the first trench.

8. The device of claim 7, further comprising a second conductive shield formed proximate to the first trench, wherein the second conductive shield is at least partially disposed within a pedestal formed over the first trench.

9. The device of claim 1, wherein the tub region further comprises a dopant within an area corresponding to a source region and within the channel region of the transistor.

10. A transistor comprising:

a tub region, wherein the tub region includes a channel region, wherein the tub region extends to a first depth, and wherein the tub region has an opposite conductivity type as a drain region;

a trench in the drain region, wherein the trench extends to a second depth, and wherein the second depth is greater than or equal to the first depth;

a dielectric layer located over at least a portion of the trench, wherein the dielectric layer is configured to reduce a field strength in proximity to the tub region; and

a pedestal located over the trench.

11. The transistor of claim 10, wherein a region of maximum or nearly maximum field strength is located at a corner region of the trench substantially below a major surface of the transistor where the dielectric layer does not experience breakdown under the maximum or nearly maximum field strength.

12. The transistor of claim 10, further comprising a first dopant of a same type as the drain region in proximity to a surface of the drain region and in proximity to the channel region to support current flow out of the channel region and into the drain region.

13. The transistor of claim 12, further comprising a second dopant implanted through a sidewall of the trench to support current flow in proximity to the trench adjacent to the sidewall of the trench.

14. The transistor of claim 10, wherein the second depth is greater than two times the first depth.

15. The transistor of claim 10, further comprising a field line edge termination.

16. The transistor of claim 10, further comprising a vertical dielectric stack adjacent to a side of the pedestal.

17. The transistor of claim 10, further comprising a first conductive shield layer formed over the trench.

18. The transistor of claim 10, further comprising a second dielectric layer and a second conductive shield layer formed over the trench.

19. The transistor of claim 10, wherein the tub region further comprises a dopant implanted within an area corresponding to a source region and within the channel region of the transistor.

20. A device comprising:

a tub region, wherein the tub region includes a channel region, wherein the tub region extends to a first depth, and wherein the tub region has an opposite conductivity type as a drain region;

a trench in the drain region, wherein the trench extends to a second depth, and wherein the second depth is greater than or equal to the first depth;

a dielectric layer located over at least a portion of the trench, wherein the dielectric layer is configured to reduce a field strength in proximity to the tub region;

a pedestal located over the trench;

a vertical dielectric stack adjacent to a side of the pedestal; and

an electrically-conductive material deposited over the pedestal, over the vertical dielectric stack, and underneath the at least a portion of the dielectric layer.