Transistor structure having a trench drain
First Claim
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1. A device comprising:
- a tub region of a transistor having a first depth, wherein the tub region includes at least a portion of a channel region of the transistor;
a first trench in a drain region of the transistor having a second depth greater than or equal to the first depth; and
a second trench formed within a surface of the first trench such that second trench is disposed below the first trench.
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Abstract
A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.
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Citations
20 Claims
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1. A device comprising:
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a tub region of a transistor having a first depth, wherein the tub region includes at least a portion of a channel region of the transistor; a first trench in a drain region of the transistor having a second depth greater than or equal to the first depth; and a second trench formed within a surface of the first trench such that second trench is disposed below the first trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A transistor comprising:
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a tub region, wherein the tub region includes a channel region, wherein the tub region extends to a first depth, and wherein the tub region has an opposite conductivity type as a drain region; a trench in the drain region, wherein the trench extends to a second depth, and wherein the second depth is greater than or equal to the first depth; a dielectric layer located over at least a portion of the trench, wherein the dielectric layer is configured to reduce a field strength in proximity to the tub region; and a pedestal located over the trench. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A device comprising:
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a tub region, wherein the tub region includes a channel region, wherein the tub region extends to a first depth, and wherein the tub region has an opposite conductivity type as a drain region; a trench in the drain region, wherein the trench extends to a second depth, and wherein the second depth is greater than or equal to the first depth; a dielectric layer located over at least a portion of the trench, wherein the dielectric layer is configured to reduce a field strength in proximity to the tub region; a pedestal located over the trench; a vertical dielectric stack adjacent to a side of the pedestal; and an electrically-conductive material deposited over the pedestal, over the vertical dielectric stack, and underneath the at least a portion of the dielectric layer.
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Specification