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Integrated circuit packaging system with vertical interconnection and method of manufacture thereof

  • US 9,093,392 B2
  • Filed: 12/10/2010
  • Issued: 07/28/2015
  • Est. Priority Date: 12/10/2010
  • Status: Active Grant
First Claim
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1. A method of manufacture of an integrated circuit packaging system comprising:

  • providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

    mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

    attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window;

    forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side above the base integrated circuit, the upper insulation having an upper insulation cavity at the upper insulation top side and in the upper insulation, wherein the upper insulation cavity provides spacing for mounting a top package within the upper insulation cavity and over the base integrated circuit;

    forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a straight non-horizontal side within the upper insulation, a peripheral connector bottom side directly on the package substrate top side, and a peripheral connector top side coplanar with the upper insulation top side, wherein the base integrated circuit is below the peripheral connector top side and exposed from the upper insulation within the upper insulation cavity; and

    mounting a top structure, having a top substrate, on the peripheral through-insulation connector, a top component attached to a top substrate bottom side of the top structure and partially within the upper insulation cavity.

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