Packaging identical chips in a stacked structure
First Claim
1. A latch chain comprising:
- a first latch chain, comprised of a single or multiple latches, associated with a first chip, the first latch chain structured to receive first address information from the first chip via a first plurality of pins; and
a second latch chain, comprised of a single or multiple latches, associated with a second chip, the second latch chain structured to receive second address information from the second chip via a second plurality of pins, wherein;
the first latch chain and the second latch chain are connected to one another such that they form a single latch chain that crosses chip boundaries; and
the first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
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Accused Products
Abstract
Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.
24 Citations
20 Claims
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1. A latch chain comprising:
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a first latch chain, comprised of a single or multiple latches, associated with a first chip, the first latch chain structured to receive first address information from the first chip via a first plurality of pins; and a second latch chain, comprised of a single or multiple latches, associated with a second chip, the second latch chain structured to receive second address information from the second chip via a second plurality of pins, wherein; the first latch chain and the second latch chain are connected to one another such that they form a single latch chain that crosses chip boundaries; and the first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A structure comprising a plurality of chips provided in a stacked configuration, wherein:
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the plurality of chips include a respective plurality of non-shared, individual signal connections arranged in a same pattern of a grid, the grid includes a plurality of rows along an “
X”
axis and a plurality of columns along a “
Y”
axis, andwhen the plurality of chips are stacked, the pattern of each of the plurality of chips is oriented to permit the respective plurality of non-shared, individual signal connections amongst the plurality of chips. - View Dependent Claims (16, 17, 18)
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19. A method comprising independent addressing of identical integrated chips in a through-silicon-via chip stack, which occurs after chip stacking;
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wherein each of the independently addressed integrated chips is identical; and each of the independently addressed integrated chips are discretely controlled by its individual, non-shared pin connections, or controlled through a global connection.
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20. A latch chain comprising:
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a first latch chain, comprised of a single or multiple latches, associated with a first chip, the first latch chain structured to read data information from the first chip; and a second latch chain, comprised of a single or multiple latches, associated with a second chip, the second latch chain structured to read data information from the second chip, wherein; the first latch chain and the second latch chain are connected to one another such that they form a single latch chain that crosses chip boundaries; the first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively , and every chip in the latch chain, including the first chip and the second chip, is identical.
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Specification