Vertical power MOSFET with planar channel and vertical field plate

• US 9,093,522 B1
• Filed: 07/22/2014
• Issued: 07/28/2015
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N., Su, Shih-Tzung, Pu, Kui
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/338,303
• Publication Number:
  US 20150221765A1
• Time in Patent Office: 371 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well'"'"'s lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.

Claims

1. A vertical transistor comprising

a semiconductor substrate having a first electrode on its bottom surface;

a first layer of a first conductivity type above the substrate, the first layer having a first dopant concentration;

a second layer of the first conductivity type above the first layer, the second layer having a second dopant concentration higher than the first dopant concentration, the second layer having a top surface;

a trench exposing a vertical sidewall of the second layer;

a well region of a second conductivity type in the top surface of the second layer, the well region having a top surface;

a first region of the first conductivity type in the top surface of the well region, wherein an area between the first region and an edge of the well region comprises a channel for inversion by a gate;

a conductive gate overlying the channel for creating a lateral conductive path between the first region and the second layer when the gate is biased above a threshold voltage;

a vertical field plate facing the vertical sidewall of the second layer and insulated from the sidewall, the vertical field plate being an extension of the gate, the vertical field plate surrounding the second layer; and

a second electrode electrically contacting the well region and the first region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a lateral current flows across the channel and a substantially vertical current flows between the channel and the substrate.

2. The transistor of claim 1 further comprising:

a third layer of the first conductivity type between the first layer and the second layer and located below the channel; and

a fourth layer of the second conductivity type laterally abutting the third layer on opposite sides of the third layer, a dopant concentration in the third layer and fourth layer being higher than the first dopant concentration.

3. The transistor of claim 2 further comprising a fifth layer of the second conductivity type below the trench and laterally adjacent to the second layer.

4. The transistor of claim 3 wherein the fifth layer abuts the fourth layer.

5. The transistor of claim 3 wherein the first layer is vertically separated from the fourth layer.

6. The transistor of claim 3 wherein the gate has a first portion overlying the channel, a second portion facing the vertical sidewall of the second layer acting as the vertical field plate, and a third portion overlying the fifth layer, wherein a thickness of a dielectric layer between the gate and the channel, the vertical sidewall, and the fifth layer is equal.

7. The transistor of claim 3 wherein the gate has a first portion overlying the channel, a second portion facing the vertical sidewall of the second layer acting as the vertical field plate, and a third portion overlying the fifth layer, wherein a thickness of a dielectric layer between the gate and the channel is less than a thickness of a dielectric layer between the gate and the fifth layer.

8. The transistor of claim 3 wherein the gate has a first portion overlying the channel, a second portion facing the vertical sidewall of the second layer acting as the vertical field plate, and a third portion overlying the fifth layer, wherein there are varying thicknesses of a dielectric layer between the gate and the vertical sidewall.

9. The transistor of claim 2 wherein the fourth layer includes a first portion below the well region, where the first portion is abutted on opposite lateral sides by the third layer.

10. The transistor of claim 9 wherein the first portion extends to the well region.

11. The transistor of claim 10 wherein a fifth layer of the first conductivity type is formed abutting lateral sides of the fourth layer and abutting a bottom surface of the fourth layer.

12. The transistor of claim 2 further comprising a fifth layer of the first conductivity type between the well region and the second layer, the fifth layer having a dopant concentration higher than that of the second layer.

13. The transistor of claim 2 further comprising:

a fifth layer of the first conductivity type below the third layer; and

a sixth layer of the second conductivity type laterally abutting the fifth layer on opposite sides of the fifth layer, the sixth layer being below the fourth layer, a dopant concentration in the fifth layer and sixth layer being higher than the first dopant concentration.

14. The transistor of claim 2 wherein the substrate is of the first conductivity type, and wherein the transistor is a MOSFET.

15. The transistor of claim 2 wherein the substrate is of the second conductivity type, and wherein the transistor is an IGBT.

16. The transistor of claim 1 wherein the gate is also located along the vertical sidewall of the second layer as the vertical field plate so as to modulate a conductivity of the vertical sidewall when the gate is biased above the threshold voltage.

17. The transistor of claim 16 wherein a first dielectric layer is located between the gate and the top surface of the well region, wherein a second dielectric layer is located between the gate and the sidewall, and wherein a thickness of the first dielectric layer is the same as the thickness of the second dielectric layer.

18. The transistor of claim 16 wherein a first dielectric layer is located between the gate and the top surface of the well region, wherein a second dielectric layer is located between the gate and the sidewall, and wherein a thickness of the first dielectric layer is less than the thickness of the second dielectric layer.

19. The transistor of claim 1 further comprising a third layer of the second conductivity type below the trench and laterally adjacent to the second layer, wherein the vertical field plate and the second dopant concentration of the second layer are configured to enhance lateral depletion of the second layer so that the second layer is fully depleted at a breakdown voltage of the transistor.

20. The transistor of claim 1 further comprising:

a third layer of the first conductivity type between the first layer and the second layer and located below the channel; and

a fourth layer of the second conductivity type laterally abutting the third layer on opposite sides of the third layer, a dopant concentration in the third layer and fourth layer being higher than the first dopant concentration,

wherein the third layer and the fourth layer form N-type and P-type columns, where the N-type and P-type columns are fully depleted at a breakdown voltage of the transistor.

21. The transistor of claim 2 wherein the third layer is more highly doped than the first layer and second layer.

22. The transistor of claim 1 further comprising a third layer of the second conductivity type below the trench and laterally adjacent to the second layer.

23. The transistor of claim 22 further comprising a conductive material in the trench and above the third layer, the conductive material being electrically connected to the second electrode.

24. The transistor of claim 1 wherein the vertical field plate is deeper than the well region.