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Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same

  • US 9,093,550 B1
  • Filed: 01/31/2013
  • Issued: 07/28/2015
  • Est. Priority Date: 01/31/2012
  • Status: Active Grant
First Claim
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1. A method of forming an integrated circuit, comprising:

  • forming, in a substrate, an NFET channel foundation, a PFET channel foundation, a DDC-NFET channel foundation, and a DDC-PFET channel foundation; and

    disposing an NFET gate stack having a first set of material layers disposed in a first order over the NFET channel foundation, disposing a PFET gate stack having a second set of material layers disposed in a second order over the PFET channel foundation, disposing a DDC-NFET gate stack having a third set of material layers disposed in a third order over the DDC-NFET channel foundation, and disposing a DDC-PFET gate stack having a fourth set of material layers disposed in a fourth order over the DDC-PFET channel foundation;

    wherein the third set of materials layers is the same as the fourth set of material layers, and the third order is the same as the fourth order;

    wherein the first set of material layers, and the second set of material layers are different from each other; and

    wherein each of the DDC-NFET and DDC-PFET channel foundations include at least a screening layer and an undoped epi layer disposed over the screening layer.

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