Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same

• US 9,093,550 B1
• Filed: 01/31/2013
• Issued: 07/28/2015
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Zhao, Dalong, Ranade, Pushkar, McWilliams, Bruce
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US13/755,887
• Time in Patent Office: 908 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02367 Substrates
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.

Claims

1. A method of forming an integrated circuit, comprising:

forming, in a substrate, an NFET channel foundation, a PFET channel foundation, a DDC-NFET channel foundation, and a DDC-PFET channel foundation; and

disposing an NFET gate stack having a first set of material layers disposed in a first order over the NFET channel foundation, disposing a PFET gate stack having a second set of material layers disposed in a second order over the PFET channel foundation, disposing a DDC-NFET gate stack having a third set of material layers disposed in a third order over the DDC-NFET channel foundation, and disposing a DDC-PFET gate stack having a fourth set of material layers disposed in a fourth order over the DDC-PFET channel foundation;

wherein the third set of materials layers is the same as the fourth set of material layers, and the third order is the same as the fourth order;

wherein the first set of material layers, and the second set of material layers are different from each other; and

wherein each of the DDC-NFET and DDC-PFET channel foundations include at least a screening layer and an undoped epi layer disposed over the screening layer.

2. The method of claim 1, wherein the second set of materials and the second order, the third set of materials and the third order, and the fourth set of materials and the fourth order are the same.

3. The method of claim 1, wherein the first set of materials and the first order, the third set of materials and the third order, and the fourth set of materials and the fourth order are the same.

4. The method of claim 1, wherein the third set of materials and the third order and the fourth set of materials and the fourth order are different from both the first set of mateials and the first order and the second set of materials and the second order.

5. The method of claim 1, wherein

disposing the NFET gate stack comprises forming a high-k dielectric layer, a tantalum nitride layer disposed over the high-k dielectric layer, a titanium nitride layer disposed over the tantalum nitride layer, and an aluminum layer disposed over the titanium nitride layer.

6. The method of claim 1, wherein forming the NFET channel foundation, the PFET channel foundation, the DDC-NFET channel foundation, and the DDC-PFET channel foundation comprises

performing well implants for all channel foundations to form NFET and PFET well regions;

performing a screen implant on the well implants for the DDC-NFET and DDC-PFET foundations to form DDC-NFET and DDC-PFET implanted regions; and

forming a substrate with substantially undoped blanket epitaxial layer disposed over the NFET and PFET well regions and DDC-NFET and DDC-PFET implanted regions.

7. The method of claim 5, wherein disposing the PFET gate stack comprises disposing a high-k dielectric layer, a titanium nitride layer disposed over the high-k dielectric layer, and an aluminum layer disposed over the titanium nitride layer.

8. The method of claim 5, disposing the DDC NFET gate stack comprises disposing a high-k dielectric layer, a titanium nitride layer disposed over the high-k dielectric layer, and an aluminum layer disposed over the titanium nitride layer.

9. The method of claim 5, disposing the DDC PFET gate stack comprises disposing a high-k dielectric layer, a titanium nitride layer disposed over the high-k dielectric layer, and an aluminum layer disposed over the titanium nitride layer.