Differential level shifter for improving common mode rejection ratio

• US 9,093,987 B1
• Filed: 09/28/2012
• Issued: 07/28/2015
• Est. Priority Date: 09/28/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Gorman, Christopher M.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US13/630,486
• Time in Patent Office: 1,033 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A differential level shifter includes: a first PMOS transistor, wherein a source/drain of the first PMOS transistor is coupled to a first CMOS signal, a gate of the first PMOS transistor is coupled to ground, and another source/drain of the first PMOS transistor is coupled to a first output node; a second PMOS transistor, wherein a source/drain of the second PMOS transistor is coupled to a second CMOS signal, a gate of the second PMOS transistor is coupled to ground, and another source/drain of the second PMOS transistor is coupled to a second output node; and a shift component coupled between the first output node and the second output node.

Claims

1. A differential level shifter, comprising:

a first PMOS transistor, wherein a source/drain of the first PMOS transistor is coupled to a first CMOS signal, a gate of the first PMOS transistor is coupled to ground, and another source/drain of the first PMOS transistor is coupled to a first output node;

a second PMOS transistor, wherein a source/drain of the second PMOS transistor is coupled to a second CMOS signal, a gate of the second PMOS transistor is coupled to ground, and another source/drain of the second PMOS transistor is coupled to a second output node; and

a shift component coupled between the first output node and the second output node

wherein the first and second PMOS transistors and the shift component are configured to convert the first and second CMOS signals into first and second output signals, the first and second output signals each having a signal swing that ranges from a power supply voltage to a voltage level greater than ground; and

wherein the first CMOS signal ranges from a first value to a second value, and wherein the differential level shifter is configured to adjust only one of the first and second values to obtain the first output signal.

2. The differential level shifter of claim 1, wherein the first CMOS signal is a positive CMOS signal and the second CMOS signal is a negative CMOS signal.

3. The differential level shifter of claim 2, wherein the negative CMOS signal is generated by inverting the positive CMOS signal.

4. The differential level shifter of claim 1, wherein the first CMOS signal and the second CMOS signal have timing differences.

5. The differential level shifter of claim 1, wherein the shift component comprises a resistor.

6. The differential level shifter of claim 1, wherein the shift component comprises a third PMOS transistor, a source/drain of the third PMOS transistor being coupled to the first output node, another source/drain of the third PMOS transistor being coupled to the second output node, and a gate of the third PMOS transistor being coupled to a control signal that configures a resistance of the third PMOS transistor.

7. The differential level shifter of claim 1, wherein the first output node is configured to provide the first output signal, and the second output node is configured to provide the second output signal.

8. The differential level shifter of claim 1, wherein the differential level shifter is configured to reduce common mode noise associated with the first and second CMOS signals.

9. A differential level shifter, comprising:

a first NMOS transistor, wherein a source/drain of the first NMOS transistor is coupled to a first CMOS signal, a gate of the first NMOS transistor is coupled to a power supply, and another source/drain of the first NMOS transistor is coupled to a first output node;

a second NMOS transistor, wherein a source/drain of the second NMOS transistor is coupled to a second CMOS signal, a gate of the second NMOS transistor is coupled to the power supply, and another source/drain of the second NMOS transistor is coupled to a second output node; and

a shift component coupled between the first output node and the second output node;

wherein the first and second NMOS transistors and the shift component are configured to convert the first and second CMOS signals into first and second output signals, the first and second output signals each having a signal swing that ranges from ground to a voltage level less than a power supply voltage; and

wherein the first CMOS signal ranges from a first value to a second value, and wherein the differential level shifter is configured to adjust only one of the first and second values to obtain the first output signal.

10. The differential level shifter of claim 9, wherein the first CMOS signal is a positive CMOS signal and the second CMOS signal is a negative CMOS signal.

11. The differential level shifter of claim 10, wherein the negative CMOS signal is generated by inverting the positive CMOS signal.

12. The differential level shifter of claim 9, wherein the first CMOS signal and the second CMOS signal have timing differences.

13. The differential level shifter of claim 9, wherein the shift component comprises a resistor.

14. The differential level shifter of claim 9, wherein the shift component comprises a third NMOS transistor, a source/drain of the third NMOS transistor being coupled to the first output node, another source/drain of the third NMOS transistor being coupled to the second output node, and a gate of the third NMOS transistor being coupled to a control signal that configures a resistance of the third NMOS transistor.

15. The differential level shifter of claim 9, wherein the differential level shifter is configured to reduce common mode noise associated with the first and second CMOS signals.

16. A method for reducing noise associated with a common mode signal, comprising:

receiving a first CMOS signal at an input of a first MOS transistor;

receiving a second CMOS signal at an input of a second MOS transistor;

reducing a first signal swing associated with the first CMOS signal to provide a first output signal at an output of the first MOS transistor by utilizing a first voltage divider formed by the first MOS transistor and a shift component coupled to the output of the first MOS transistor; and

reducing a second signal swing associated with the second CMOS signal to provide a second output signal at an output of the second MOS transistor by utilizing a second voltage divider formed by the second MOS transistor and the shift component, wherein the shift component is coupled to the output of the second MOS transistor;

wherein the first CMOS signal ranges from a first value to a second value, and wherein only one of the first and second values is adjusted to obtain the first output signal;

the first output signal and the second output signal each having a signal swing that ranges from a power supply voltage to a voltage level greater than ground, or from the ground to a voltage level less than the power supply.