Slew based process and bias monitors and related methods

• US 9,093,997 B1
• Filed: 11/15/2013
• Issued: 07/28/2015
• Est. Priority Date: 11/15/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Kidd, David A., Boling, Edward J., Agrawal, Vineet, Leshner, Samuel, Kuo, Augustine, Lee, Sang-Soo, Chen, Chao-Wu
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US14/081,264
• Time in Patent Office: 620 Days
• Field of Search: 327/142, 327/143, 327/198, 327164-180, 327108-112, 327/379, 327/389, 327/391, 327534-535, 327/537, 326 22- 27, 326 81- 87
• US Class Current: 1/1
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 5/04 by increasing duration; by decreasing duration
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals

Abstract

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Claims

1. An integrated circuit, comprising:

at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor;

a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal;

a counter configured to generate a count value corresponding to a duration of the first pulse; and

a pulse extender circuit coupled to receive the pulse signal and configured to generate an extended pulse signal with an extended pulse;

wherein

the duration of the extended pulse is proportional to the duration of the first pulse.

2. The integrated circuit of claim 1, wherein:

the at least one reference transistor includes a heavily doped region to which a body bias is coupled.

3. The integrated circuit of claim 1, wherein:

the at least one reference transistor further includes a body region, a substantially undoped channel and a doped screening region formed under the substantially undoped channel and above the body region, the screening region being doped to a higher concentration than the body region.

4. The integrated circuit of claim 1, further including:

circuits configured to adjust the operating characteristics of other transistors of the integrated circuit based on the duration of the first pulse, the characteristic selected from the group of;

transistor speed and transistor power consumption.

5. The integrated circuit of claim 1, wherein:

the counter increments a count value during the duration of the extended pulse.

6. The integrated circuit of claim 1, wherein:

the at least one slew generator circuit includes

an n-channel slew generator circuit configured to generate the first signal, and a slew rate of the first signal varies according to the operation of an n-channel reference transistor, and

a p-channel slew generator circuit configured to generate a second signal, and a slew rate of the second signal varies according the operation of a p-channel reference transistor;

wherein

the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors.

7. The integrated circuit of claim 1, further comprising:

at least one body bias control circuit configured to generate a body bias voltage for other transistors of the integrated circuit that varies in response to the count value.

8. An integrated circuit, comprising:

at least one slew generator circuit comprising at least one reference transistor, the slew generator circuit configured to generate at least a first slew signal having a slew rate that varies according to characteristics of the reference transistor, the at least one slew generator circuit including

an n-channel slew generator circuit configured to generate the first pulse signal with a pulse having a duration that varies according to the operation of an n-channel reference transistor, and

a p-channel slew generator circuit configured to generate a second pulse signal having a pulse duration that varies according the operation of a p-channel reference transistor;

a pulse generator circuit coupled to receive the first slew signal and configured to drive a pulse signal to a first value when a level of the first slew signal is within first and second limits, and configured to drive the pulse signal to a second value when the level of the first slew signal is outside of the first and second limits; and

a counter configured to generate a count value corresponding to a duration of the pulse signal at the first value;

wherein

the integrated circuit includes other circuits that include transistors fabricated with the same process as the n-channel and p-channel reference transistors.

9. The integrated circuit of claim 8, wherein:

the at least one slew generator comprises a load capacitor coupled to the source-drain path of the at least one reference transistor;

the pulse generator circuit includes

a first comparator having one input coupled to receive a voltage from the load capacitor, and a second input coupled to a first limit voltage,

a second comparator having one input coupled to receive the voltage from the load capacitor, and a second input coupled to a second limit voltage, and

logic circuits coupled to outputs of the first and second comparators, and configured to output the pulse signal.

10. The integrated circuit of claim 8, wherein:

the at least one reference transistor includes a body region and a screening region formed under a substantially undoped channel, the screening region positioned between the substantially undoped channel and the body region, with the screening region being doped to a higher concentration than body region.

11. An integrated circuit, comprising:

at least one slew generator circuit comprising at least one reference transistor having an undoped channel, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor;

a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and

a pulse extender circuit configured to generate a second pulse in response to a capacitor voltage, the pulse extender circuit including

a first section configured to generate a change in the capacitor voltage from an initial voltage to a changed voltage, the change in capacitor voltage being proportional to a duration of the first pulse, and

a current source configured to enable a current path to cause the capacitor voltage to return toward the initial voltage from the changed voltage.

12. The integrated circuit of claim 11, wherein:

the first section includes a controllable current path that enables a current of a first magnitude to flow in a first direction with respect to the capacitor having the capacitor voltage; and

the current source includes a current path that enables a current of a second magnitude to flow in a second direction with respect to the capacitor;

wherein

the difference between the first magnitude and the second magnitude correspond to the difference between the duration of the first pulse and the duration of the second pulse.

13. The integrated circuit of claim 11, wherein:

the at least one reference transistor includes a body region and a screening region formed under the undoped channel, the screening region positioned between the undoped channel and the body region, with the screening region being doped to a higher concentration than body region.

14. The integrated circuit of claim 11, wherein:

the pulse extender circuit further includes a comparator circuit having a first input coupled to capacitor voltage and a second input coupled to a reference voltage.

15. The integrated circuit of claim 11, further including:

at least one body bias control circuit configured to generate a body bias voltage for other transistors of the integrated circuit that varies in response to the duration of the extended pulse.