High-speed signaling systems with adaptable pre-emphasis and equalization

• US 9,094,238 B2
• Filed: 08/23/2011
• Issued: 07/28/2015
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Chen, Fred F., Ho, Andrew, Farjad-Rad, Ramin, Poulton, John W., Donnelly, Kevin S., Leibowitz, Brian S.
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US13/216,047
• Publication Number:
  US 20110305271A1
• Time in Patent Office: 1,435 Days
• Field of Search: 375229-233, 375/259, 375/295, 375/316
• US Class Current: 1/1
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04W 52/20 using error rate
• CPC Class Codes: H04W 52/225 Calculation of statistics, e.g. average, variance
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Claims

1. A first integrated circuit, comprising:

a linear equalizer to receive a digital bit stream from a second integrated circuit over a signal path and to equalize the digital bit stream and generate an output; and

a decision feedback equalizer having a tap, the tap driven based on a historical data value conveyed by the digital bit stream, the decision feedback equalizer to equalize the output;

where the first integrated circuit has two equalization modes, including a first mode where the tap is used to equalize data received from the second integrated circuit, and a second mode where the tap is disabled and is not used to equalize the data received from the second integrated circuit; and

where a selection between the first and the second modes is made based on a relative circuit power parameter between the first and the second modes and irrespective of characteristics of the signal path.

2. The first integrated circuit of claim 1, where the decision feedback equalizer is a multi-tap decision feedback equalizer.

3. The first integrated circuit of claim 2, where the multi-tap decision feedback equalizer includes a partial response decision feedback equalizer and at least one infinite impulse response filter tap, each infinite impulse response filter tap driven in response to an interpreted historical data value conveyed by the digital bit stream.

4. The first integrated circuit of claim 3, where in the first mode, plural taps of the multi-tap decision feedback equalizer are used to equalize the data received from the second integrated circuit, and in the second mode, a subset of the plural taps is used to equalize the data received from the second integrated circuit, and each remaining tap outside of the subset is disabled and is not used to equalize the data received from the second integrated circuit.

5. The first integrated circuit of claim 4, further comprising mode circuitry to disable at least one of the plural taps during the second mode.

6. The first integrated circuit of claim 4, where the decision feedback equalizer has two feedback paths, where in the first mode each of the two feedback paths is enabled, and where in the second mode, only a first one of the two feedback paths is enabled and a second one of the two feedback paths is disabled.

7. The first integrated circuit of claim 6, where the linear equalizer has a control input to adjust a degree to which the linear equalizer amplifies high frequency signals relative to low frequency signals.

8. The first integrated circuit of claim 7, where the control input provides a digital control value adjustable over at least sixteen steps.

9. The first integrated circuit of claim 8, where a performance monitor of the first integrated circuit is to obtain a measure of signal quality for each of plural settings for the linear equalizer and is to compare the measures of signal quality to a threshold, and where a setting is to be selected for the linear equalizer such that the corresponding measure of signal quality meets the threshold and such that the setting represents a minimum power consumption relative to the any other setting for the linear equalizer where the corresponding measure exceeds the threshold.

10. The first integrated circuit of claim 9, further comprising:

at least one edge sampler;

at least one data sampler; and

clock recovery circuitry to recover a timing signal from the digital bit stream.

11. The first integrated circuit of claim 1, where the first integrated circuit receives the digital bit stream as a serial, differential input signal.

12. The first integrated circuit of claim 1, further comprising a controller, the controller to select one of the first mode and the second mode, and further, to define equalization settings for the second integrated circuit.

13. The first integrated circuit of claim 12, where:

the data to be received by the first integrated circuit from the second integrated circuit is first data;

the first integrated circuit further comprises a transmitter to transmit second data from the first integrated circuit and circuitry to equalize the second data, the circuitry having a transmit tap; and

in the first mode, the decision feedback equalizer tap and the transmit tap are used to equalize the second data, and in the second mode, a subset of taps of the group of (a) the decision feedback equalizer tap and (b) the transmit tap are used to equalize the second data, and each remaining tap outside of the subset is disabled.

14. The first integrated circuit of claim 13, where the transmit tap in the first mode equalizes only for pre-tap interference.

15. A method, comprising:

receiving a digital bit stream from an integrated circuit over a signal path; and

equalizing the digital bit stream according to a selective one of two equalization modes;

where

in a first one of the equalization modes, equalizing includes using a linear equalizer to equalize the digital bit stream and generate an output and using a decision feedback equalizer having a tap to equalize the output, the tap driven based on a historical data value conveyed by the digital bit stream,

in a second one of the equalization modes, equalizing includes using the linear equalizer to equalize the digital bit stream, but disabling the tap and not using the tap to equalize data received from the integrated circuit, and

where a selection between the first and the second one of the equalization modes is made based on a relative circuit power parameter between the first and the second equalization modes and irrespective of characteristics of the signal path.

16. The method of claim 15, where the decision feedback equalizer includes multiple taps and where in the second mode, one of the multiple taps is disabled.

17. The method of claim 16, where the decision feedback equalizer includes a partial response decision feedback equalizer and at least one infinite impulse response filter tap, each infinite impulse response filter tap driven in response to an interpreted historical data value conveyed by the digital bit stream, and where:

in the first one of the equalization modes, plural taps of the multiple taps are used to equalize the data received from the integrated circuit; and

in the second one of the equalization modes, only a subset of the multiple taps are used to equalize data received from the integrated circuit, each remaining tap outside of the subset being disabled and not used to equalize the data received from the integrated circuit in the second mode.

18. The method of claim 17, where the decision feedback equalizer has two feedback paths, the method further comprising:

in the first equalization mode, enabling each of the two feedback paths; and

in the second equalization mode, enabling only a first one of the two feedback paths and disabling a second one of the two feedback paths.

19. The method of claim 18, where the linear equalizer has a control input, the method further comprising using the control input to adjust a degree to which the linear equalizer amplifies high frequency signals relative to low frequency signals.

20. The method of claim 19, where the control input provides a digital control value adjustable over at least sixteen steps.

21. The method of claim 19, further comprising:

obtaining a measure of signal quality for each of plural settings for the linear equalizer;

comparing the measures of signal quality to a threshold; and

selecting a setting for the linear equalizer such that the corresponding measure of signal quality meets the threshold and such that the setting represents a minimum power consumption relative to any others of the plural settings for which a corresponding measure meets the threshold.

22. The method of claim 21, further comprising using at least one edge sampler, at least one data sampler, and clock recovery circuitry to recover a timing signal from the digital bit stream.

23. The method of claim 15, further comprising receiving the digital bit stream as a serial, differential input signal.

24. The method of claim 15, where the integrated circuit is a second integrated circuit and where the method is embodied in a first integrated circuit, the method further comprising using a controller resident in the first integrated circuit to select one of the first equalization mode and the second equalization mode, and further, to define equalization settings for the second integrated circuit.

25. The method of claim 15, where:

the integrated circuit is a second integrated circuit;

the method is embodied in first integrated circuit;

the data to be received by the first integrated circuit from the second integrated circuit is first data;

the method further comprises using a transmit equalizer having a transmit tap to equalize second data transmitted to the second integrated circuit;

in the first one the equalization modes, a specific pre-cursor latency is used by the transmit tap to equalize the second data, and the tap of the decision feedback equalizer is used to equalize the first data according to a specific post-cursor latency;

in the second one of the equalization modes, the specific post-cursor latency is used by the transmit equalizer to equalize the second data, and the tap of the decision feedback equalizer is not used to equalize the first data.

26. A first integrated circuit, comprising:

a receiver to receive a digital bit stream from a second integrated circuit over a signal path;

a linear equalizer; and

means for using decision feedback equalization to equalize the digital bit stream according to a selected one of two equalization modes, where in a first one of the equalization modes, the means equalizes according to a specific latency and in a second one of the equalization modes, the means does not equalize according to the specific latency;

where a selection between the first and the second equalization modes is made based on a relative circuit power parameter between the first and the second equalization modes and irrespective of characteristics of the signal path.