Structure for microelectronic packaging with bond elements to encapsulation surface

• US 9,095,074 B2
• Filed: 10/17/2014
• Issued: 07/28/2015
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Haba, Belgacem, Mohammed, Ilyas, Caskey, Terrence, Co, Reynaldo, Chau, Ellis
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US14/517,268
• Publication Number:
  US 20150034371A1
• Time in Patent Office: 284 Days
• Field of Search: 257/686, 257/693, 257/697, 257700-702, 257/E23.024, 257/E25.006, 257/E25.021, 257/E25.027, 257/E23.085, 438/106, 438/109, 438/111, 438/112
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1191 Forming a passivation layer after forming the bump connector
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45012 : Cross-sectional shape
• CPC Class Codes: H01L 2224/45014 : Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45101 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/45624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45655 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3157 : Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15322 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/11 : Printed elements for providing electric connections to or between printed circuits
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Claims

1. A structure comprising:

a substrate having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the first surface;

wire bonds having bases joined to respective ones of the conductive elements at a first portion of the first surface and end surfaces remote from the substrate and the bases, each of the wire bonds extending from the base to the end surface thereof; and

a dielectric encapsulation element overlying and extending from the first portion of the first surface of the substrate and separating the wire bonds from one another, the encapsulation element having a third surface facing away from the first surface of the substrate and having an edge surface extending from the third surface towards the first surface, wherein unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation element at the third surface;

wherein the encapsulation element at least partially defines a second portion of the first surface, the second portion being other than the first portion of the first surface and having an area sized to accommodate a microelectronic element, and at least some of the conductive elements at the first surface are at the second portion and configured for connection with the microelectronic element.

2. The structure of claim 1, wherein a portion of at least one the wire bonds extending above the third surface is non-parallel to the third surface.

3. The structure of claim 1 further comprising:

solder at at least one of the base or the end surface of at least one of the wire bonds.

4. The structure of claim 3, wherein the solder at the end surface of the at least one wire bond is at the third surface.

5. The structure of claim 3, wherein the solder extends from the end surface of the at least one wire bond through a portion of the encapsulation element towards the third surface.

6. The structure of claim 1, wherein at least a portion of at least one of the wire bonds adjacent the end surface thereof is non-parallel to the third surface.

7. The structure of claim 1, wherein the substrate is a semiconductor substrate including electrical interconnections therein.

8. The structure of claim 1, wherein at least one of the wire bonds includes a stud bump joined to the end surface thereof.

9. The structure of claim 1, wherein at least one of the wire bonds extends along a substantially straight line between the base and the unencapsulated portion thereof, and wherein the substantially straight line forms an angle of less than 90°

with respect to the first surface of the substrate.

10. The structure of claim 1, wherein at least one of the wire bonds includes a substantially curved portion between the base and the end surface thereof.

11. A method of making a structure comprising:

forming a dielectric encapsulation element on a substrate, the substrate having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the first surface, and wherein wire bonds are joined at bases thereof to respective ones of the conductive elements at a first portion of the first surface and end surfaces of the wire bonds are remote from the substrate and the bases, each of the wire bonds extending from the base to the end surface thereof,

wherein the dielectric encapsulation element is formed overlying and extending from the first portion of the first surface of the substrate and separating the wire bonds from one another, the encapsulation element having a third surface facing away from the first surface of the substrate and having an edge surface extending from the third surface towards the first surface, wherein unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation element at the third surface, and

wherein the encapsulation element at least partially defines a second portion of the first surface, the second portion being other than the first portion of the first surface and having an area sized to accommodate a microelectronic element, and at least some of the conductive elements at the first surface are at the second portion and configured for connection with the microelectronic element.

12. The method of claim 11, wherein a portion of at least one the wire bonds extending above the third surface is non-parallel to the third surface.

13. The method of claim 11, wherein at least one of the wire bonds is joined at the base thereof to one of the conductive elements before the encapsulation element is formed on the substrate.

14. The method of claim 11, wherein at least one of the wire bonds is soldered at the base thereof to one of conductive elements before the encapsulation element is formed on the substrate.

15. The method of claim 14, wherein the solder extends from the end surface of the at least one wire bond through a portion of the encapsulation element towards the third surface.

16. The method of claim 11, wherein at least a portion of at least one of the wire bonds adjacent the end surface thereof is non-parallel to the third surface.

17. The method of claim 11, wherein the substrate is a semiconductor substrate including electrical interconnections therein.

18. The method of claim 11, wherein at least one of the wire bonds includes a stud bump joined to the end surface thereof.

19. The method of claim 11, wherein at least one of the wire bonds extends along a substantially straight line between the base and the unencapsulated portion thereof, and wherein the substantially straight line forms an angle of less than 90°

with respect to the first surface of the substrate.

20. The method of claim 11, wherein at least one of the wire bonds includes a substantially curved portion between the base and the end surface thereof.