Multi-input memory command prioritization

• US 9,098,203 B1
• Filed: 11/19/2012
• Issued: 08/04/2015
• Est. Priority Date: 03/01/2011
• Status: Active Grant

• Current Assignee: Marvell Israel MISL Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell Israel MISL Limited (Marvell Technology Group Limited)
• Inventors: Kedem, Ron
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US13/681,124
• Time in Patent Office: 988 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling

Abstract

Embodiments of the present disclosure provide a method and system for prioritizing memory commands. A priority determination engine determines a priority of a memory access command based on a plurality of inputs related to characteristics of the memory access command and a plurality of inputs related to a state of the memory. An access scheduler selects an order in which to issues the memory commands based at least on the priority. The priority determination is determined such that bandwidth utilization is improved.

Claims

1. A system on a chip comprising:

a buffer configured to hold a queued plurality of memory access commands;

a priority determination engine that is configured to determine a priority of a memory access command of the plurality of memory access commands in the queue, and to determine the priority based at least on a weight that is indicative of a magnitude of a memory access overhead penalty of the memory access command; and

an access scheduler configured to select an order for the plurality of memory access commands to be issued to the memory based at least on the corresponding priority of the memory access command.

2. The system on a chip of claim 1, wherein the priority determination engine is further configured to determine the priority of the memory access command based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory, wherein the second inputs related to the state of the memory are determined at least from a history of memory access.

3. The system on a chip of claim 1, wherein the priority determination engine is further configured to determine the priority of the memory access command based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory, wherein the second inputs related to the state of the memory are determined at least from characteristics of a previously issued command, wherein the characteristics of the previously issued command include one or more of a memory page accessed according to the previously issued command, a bank accessed according to the previously issued command, a chip select accessed according to the previously issued command, or a command type of the previously issued command.

4. The system on a chip of claim 1, wherein the priority determination engine is further configured to determine the priority of the memory access command based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory, wherein the state of the memory includes one or more of a state of a memory bank or a state of a memory row.

5. The system on a chip of claim 1, wherein the priority determination engine is further configured to determine the priority of the memory access command based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory, wherein the state of the memory includes one or more of:

information regarding one or more open memory banks;

information regarding one or more closed memory banks;

information regarding one or more open memory pages;

or

information regarding one or more closed memory pages.

6. The system on a chip of claim 1, wherein the priority determination engine is further configured to determine the priority based at least further on first inputs related to characteristics of the memory access command, second inputs related to a state of a memory, and a comparison of at least one of the first inputs to a corresponding one of the second inputs.

7. The system on a chip of claim 6, wherein the priority determination engine is further configured to apply the weight to a result of the comparison.

8. The system on a chip of claim 1, wherein the weight is user-programmable.

9. The system on chip of claim 1, wherein the weight is a first weight, the magnitude is a first magnitude, the memory access overhead penalty is a first memory access overhead penalty associated with a first characteristic of the memory access command, and the priority determination engine is further configured to:

determine the priority of the memory access command based at least on first inputs related to characteristics of the memory access command and on second inputs related to a state of a memory, the characteristics of the memory access command including the first characteristic;

compare a first one of the first inputs related to the first characteristic of the memory access command to a corresponding first one of the second inputs to determine a first comparison result;

compare a second one of the first inputs related to a second characteristic of the memory access command to a corresponding second one of the second inputs to determine a second comparison result;

multiply the first comparison result by the first weight to determine a first product;

multiply the second comparison result by a second weight to determine a second product, the second weight indicative of a second magnitude of a second memory access overhead penalty associated with the second characteristic of the memory access command; and

sum at least the first product and the second product to determine the priority.

10. The system on a chip of claim 9, wherein the priority determination engine is further configured to select a third weight based on a third one of the first inputs, and sum the third weight, the first product, and the second product to determine the priority.

11. The system on a chip of claim 1, wherein the buffer is divided into a plurality of queues, wherein ones of the queues correspond to ones of a plurality of banks of the memory.

12. A method comprising:

receiving a plurality of memory access commands that correspond to a plurality of memory operations to be performed on a memory;

determining a priority for one of the memory access commands based at least on a weight that is indicative of a magnitude of a memory access overhead penalty of the memory access command; and

based at least on the determined priority, determining a next one of the plurality of memory access commands to be issued to the memory bus.

13. The method of claim 12, further comprising determining the priority based further on first inputs related to characteristics of the one of the memory access commands and second inputs related to a state of a memory bus of the memory, wherein the second inputs related to the state of the memory bus are determined at least from characteristics of a previously issued command.

14. The method of claim 12, further comprising determining the priority based further on first inputs related to characteristics of the one of the memory access commands and second inputs related to a state of a memory bus of the memory, including comparing at least a first one of the first inputs to a corresponding first one of the second inputs and applying the weight to a result of the comparing.

15. The method of claim 14, wherein the memory is a double data rate 3 synchronous dynamic random-access memory (DDR3 SDRAM).

16. The method of claim 12, wherein the weight is configurable.

17. The method of claim 14, wherein the result of the comparing indicates an access scenario, including at least one of:

consecutive access to an open page of a memory bank;

access to a closed page of a different memory bank;

consecutive access to a dual in-line memory module; and

consecutive read operations or consecutive write operations.

18. The method of claim 12, wherein the state of the memory bus includes one or more of:

information regarding open or closed memory banks;

information regarding open or closed memory pages;

information regarding a recently accessed dual in-line memory module or

information regarding a command type of a recently issued memory access command.

19. The method of claim 12, further comprising determining the priority based further on first inputs related to characteristics of the one of the memory access commands and second inputs related to a state of a memory bus of the memory, wherein the characteristics of the one of the memory access commands includes one or more of:

information regarding a memory bank to be accessed according to the at least one of the memory access commands;

information regarding a memory page to be accessed according to the at least one of the memory access commands;

information regarding a dual in-line memory module to be accessed according to the at least one of the memory access commands; and

information regarding a command type of the at least one of the memory access commands.