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Multi-input memory command prioritization

  • US 9,098,203 B1
  • Filed: 11/19/2012
  • Issued: 08/04/2015
  • Est. Priority Date: 03/01/2011
  • Status: Active Grant
First Claim
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1. A system on a chip comprising:

  • a buffer configured to hold a queued plurality of memory access commands;

    a priority determination engine that is configured to determine a priority of a memory access command of the plurality of memory access commands in the queue, and to determine the priority based at least on a weight that is indicative of a magnitude of a memory access overhead penalty of the memory access command; and

    an access scheduler configured to select an order for the plurality of memory access commands to be issued to the memory based at least on the corresponding priority of the memory access command.

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