Device and method of establishing sleep mode architecture for NVSRAMs

• US 9,098,270 B1
• Filed: 12/29/2011
• Issued: 08/04/2015
• Est. Priority Date: 11/01/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Still, David, Tiyyagura, SrikanthReddy
• Primary Examiner(s): Rehman, Mohammed
• Application Number:
  US13/340,453
• Time in Patent Office: 1,314 Days
• Field of Search: 713/323
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A device is configured to establish first and second device power domains. Isolation circuits isolate signals from passing between circuits in the first device power domain and circuits in the second device power domain. During a transition between power domains, an n-bit value is stored in a particular storage location, and compared to a particular n-bit value. Isolation between the first and second device power domains is removed when the n-bit value stored in the particular storage location matches the particular n-bit value.

Claims

1. A method of operating a device alternatively in a normal power mode, an auto-store power mode and a sleep power mode, wherein the device is configured to be divided into a normal, an auto-store and a sleep power domains, the method comprising:

receiving an indication at the sleep power domain to transition the device from the sleep power mode into the normal power mode;

monitoring a state of the auto-store power domain during the transition;

storing an n-bit semaphore value by a controller in a particular storage location in the auto-store power domain when the state of the auto-store power domain is such that reliable data transfer may take place to and from circuits outside of the auto-store power domain;

monitoring contents of the particular storage location in an ongoing fashion, wherein the particular storage location is a register; and

removing isolation for signals to and from the auto-store power domain.

2. The method of claim 1, further comprising:

resetting contents of the particular storage location while transitioning into the sleep power mode from the normal or the auto-store power mode wherein an n-bit reset value different from the n-bit semaphore value is stored in the particular storage location.

3. The method of claim 1, further comprising:

disconnecting both a primary and backup power sources from powering circuits in the normal and the auto-store power domains of the device when transitioning into the sleep power mode.

4. A method of operating a device in a normal power mode, an auto-store power mode and a sleep power mode selectively and alternatively, the method comprising:

establishing a normal and an auto-store power domains in the device;

isolating, using isolation logic, circuits in the normal power domain from circuits in the auto-store power domain;

storing, using a controller, an n-bit value in a particular storage location wherein n is greater than 1;

comparing, using control logic, the n-bit value stored in the particular storage location with a predetermined particular n-bit semaphore value; and

removing isolation, using the isolation logic, between the normal and the auto-store power domains when the n-bit value stored in the particular storage location matches the predetermined particular n-bit semaphore value.

5. The method of claim 4, further comprising:

removing one or more of inbound and outbound isolation between the auto-store power domain and the normal power domain when the n-bit value stored in the particular storage location matches the predetermined particular n-bit semaphore value.

6. The method of claim 5, further comprising:

establishing a

sleep power domain; and

disconnecting both primary and backup power sources from powering circuits in the normal and auto-store power domains of the device when transitioning into the Sleep power mode.

7. The method claim 4, further comprising:

causing the controller to load the predetermined particular n-bit semaphore value into the particular storage location when, during a transition from the Sleep power mode to the Normal power mode, the device auto-store power domain reaches a state in which data can be reliably transferred between circuits in the normal power domain and the device auto-store power domain.

8. The method of claim 4 wherein the particular storage location is a register, further comprising:

providing the n-bit value stored in the register to the control logic;

outputting a signal from the control logic to remove isolation for signals to and from the auto-store power domain when the n-bit value stored in the register matches the predetermined particular n-bit semaphore value.

9. The method of claim 4, further comprising:

storing an n-bit garbage value in the particular storage location when data transfer between the normal and the auto-store power domains is unreliable, the n-bit garbage value having a low probability of being equal to the predetermined particular n-bit semaphore value.

10. The method of claim 4, wherein the second device power domain includes at least one nvSRAM circuit.

11. A device configured to operate selectively and alternatively in a normal power mode, an auto-store power mode and a sleep power mode, the device comprising:

a first device power domain that is a normal power domain; and

a second device power domain that is an auto-store power domain, wherein the second device power domain includes;

at least one isolation logic configured to provide isolation between circuits in the first device power domain and circuits in the second device power domain,

a controller configured to store an n-bit value in a register logic,

a control logic configured to compare the n-bit value stored in the register logic with a particular n-bit semaphore value and control operation of the at least one isolation logic, wherein the isolation logic is to remove the isolation between the circuits of the first and second device power domains when the n-bit value stored in the register logic matches the particular n-bit semaphore value.

12. The device of claim 11, wherein:

the first and second device power domains are powered by a main power during the normal power mode, wherein the circuits in the first and the second device power domains are not isolated,

the second device power domain is powered by a back up power during the auto-store power mode when the main power supply drops below a power threshold, wherein the circuits in the first and the second device power domains are isolated, and

the second power domain and most of the circuits in the first power domain are unpowered during the sleep mode, wherein the circuits in the first and the second device power domains are isolated.

13. The device of claim 11, wherein the device further includes a third device power domain that is a sleep power domain, the third device power domain comprising:

a wake up logic which is only powered during the sleep power mode; and

selective circuits in the first device power domain, wherein the selective circuits are powered by the main power during the normal mode,

wherein the wake up logic and the selective circuits in the first device power domain are coupled and powered by at least one power source other than the main power and the back up power during the sleep mode.

14. The device of claim 13 during transition into the sleep power mode, wherein the wake up logic is powered and configured to:

store a n-bit reset value which is different from the particular n-bit semaphore value in the register logic; and

disconnect the first and second device power domains from the main and back up power.

15. The device of claim 13 during transition out of the sleep power mode, wherein the wake up logic is configured to restore connection between the first and second device power domains from the main and back up power to cause the controller to store the particular n-bit semaphore value in the register logic.

16. The device of claim 11, wherein the isolation between circuits in the first device power domain and circuits in the second device power domain is one-way.

17. The device of claim 11, wherein the isolation between circuits in the first device power domain and circuits in the second device power domain is two-way.

18. The device of claim 11, wherein the second device power domain further includes at least one non-volatile static random-access memory (nvSRAM) circuit coupled to the controller.