Providing silicon integrated code for a system

• US 9,098,300 B2
• Filed: 07/05/2013
• Issued: 08/04/2015
• Est. Priority Date: 06/25/2010
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Xing, Bin, Robinson, Scott H.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Hicks, Austin
• Application Number:
  US13/935,767
• Publication Number:
  US 20140013095A1
• Time in Patent Office: 760 Days
• Field of Search: 713/503
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a non-volatile storage to store semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer, the platform independent code to be executed regardless of characteristics of a platform including a processor of the processor manufacturer, the SIC including an embedded processor logic to initialize the processor and at least one communication link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to pre-boot code of an original equipment manufacturer (OEM), wherein the SIC is included in the non-volatile storage, the non-volatile storage including OEM basic input/output system (BIOS), the OEM BIOS dependent on the characteristics of the platform, and a plurality of SIC versions, each associated with a corresponding SIC data module, wherein an initial program loader (IPL) is to select one of the plurality of SIC versions and SIC data modules to launch.

2. The apparatus of claim 1, further comprising an initial program loader (IPL) to load the SIC, the IPL to be launched from microcode of the processor, wherein the IPL is to authenticate the SIC and then to launch the SIC.

3. The apparatus of claim 2, wherein the IPL is to access a firmware interface table (FIT) having an entry including a pointer to point to a location of the SIC.

4. The apparatus of claim 3, wherein the SIC is provided as a binary to the OEM for inclusion in the non-volatile storage.

5. The apparatus of claim 1, wherein the SIC data module includes processor manufacturer data provided by the processor manufacturer, OEM data provided by the OEM, and end user data provided by an end user, wherein the OEM data and the end user data is platform dependent.

6. The apparatus of claim 5, wherein the OEM data is trusted data that is signed by the processor manufacturer prior to insertion into the non-volatile storage.

7. The apparatus of claim 1, wherein the non-volatile storage is of a processor package including a plurality of cores, at least one microcode store, and an integrated memory controller.

8. The apparatus of claim 1, wherein the SIC is to sequester a portion of the system memory for the processor, wherein the sequestered portion is to be invisible to an operating system.

9. The apparatus of claim 8, wherein the processor is to store a binary translator in the sequestered portion.

10. At least one non-transitory computer-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving an indication in a system during runtime that at least one component is to be dynamically incorporated into the system;

triggering a power management operation via operating system power management (OSPM) code responsive to the indication;

invoking semiconductor integrated code (SIC) from the OSPM code and without entry into a system management mode, the SIC corresponding to platform independent code of a processor manufacturer, and executing initialization of the at least one component using the SIC, wherein the SIC comprises a plurality of SIC versions, each associated with a corresponding SIC data module; and

unloading the SIC and returning to the OSPM, wherein the SIC is provided as a binary module by the processor manufacturer to an original equipment manufacturer (OEM) of the system.

11. The at least one non-transitory computer-readable medium of claim 10, further comprising instructions to enable the system to access a SIC data module using the SIC, based on an entry in a firmware interface table (FIT).

12. The at least one non-transitory computer-readable medium of claim 11, further comprising instructions to enable the system to execute the initialization using information in the SIC data module.

13. The at least one non-transitory computer-readable medium of claim 10, further comprising instructions to enable the system to, the SIC to perform initialization of a processor and memory of the system on system startup.

14. The at least one non-transitory computer-readable medium of claim 13, further comprising instructions to enable the system to, after performing the initialization, store the SIC in a sequestered portion of the memory setup by the SIC.

15. The at least one non-transitory computer-readable medium of claim 14, further comprising instructions to enable the system to invoke the SIC stored in the sequestered portion.

16. The at least one non-transitory computer-readable medium of claim 10, further comprising instructions to enable the system to synthesize a peripheral device address in a chipset and invoke the SIC via an access to the peripheral device address by the OSPM code.

17. A system comprising:

a processor including a plurality of cores, a microcode storage, and a memory controller;

a peripheral controller coupled to the processor;

a trusted platform module coupled to the processor; and

a non-volatile memory to store semiconductor integrated code (SIC) corresponding to platform independent code of a manufacturer of the processor, the platform independent code to be executed regardless of characteristics of the system, the SIC including an embedded processor logic to initialize the processor and at least one link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to an original equipment manufacturer (OEM) basic input/output system (BIOS) firmware included in the non-volatile memory, the OEM BIOS dependent on the characteristics of the system, wherein the SIC is selected by an initial program loader (IPL) from a plurality of SIC versions stored in the non-volatile memory, each of the plurality of SIC versions associated with a corresponding SIC data module; and

the system memory coupled to the processor.

18. The system of claim 17, further comprising the IPL to authenticate and then launch the SIC, the IPL to be launched from microcode of the processor stored in the system memory.

19. The system of claim 18, wherein the SIC is to sequester a portion of the system memory for exclusive use by the processor during system operation, wherein the sequestered portion is to be invisible to an operating system.