Specialized processing block with fixed- and floating-point structures

• US 9,098,332 B1
• Filed: 06/01/2012
• Issued: 08/04/2015
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US13/486,255
• Time in Patent Office: 1,159 Days
• Field of Search: 708/501, 708/503, 708/505, 708/513, 708/518, 708/714
• US Class Current: 1/1
• CPC Class Codes: G06F 2207/3824 Accepting both fixed-point and floating-point numbers
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/485 Adding; Subtracting G06F7/4833, G06F7/4836 take precedence
• CPC Class Codes: G06F 7/49936 Normalisation mentioned as feature only
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 7/49957 Implementation of IEEE-754 Standard
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30014 with variable precision

Abstract

Circuitry for performing arithmetic operations on a plurality of inputs efficiently performs both fixed-point operations and floating-point operations. Each of at least first and second respective operator circuits operates on a respective subplurality of the plurality of inputs. Other circuitry selectively interconnects the respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) the full plurality of inputs, (b) individual ones of the respective subpluralities of the plurality of inputs, or (c) combinations of portions of the respective subpluralities of the plurality of inputs. At least one of the respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among the multiple different results based on an output of another one of the respective operator circuits. One or more of the multiple different results are selectably usable to perform both fixed-point operations and floating-point operations.

Claims

1. Circuitry for performing arithmetic operations on a plurality of inputs, said circuit comprising:

at least first and second respective operator circuits, each of said at least first and second respective operator circuits operating on a respective subplurality of said plurality of inputs; and

circuitry for selectively interconnecting said at least first and second respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) said full plurality of inputs, (b) individual ones of said respective subpluralities of said plurality of inputs, or (c) combinations of portions of said respective subpluralities of said plurality of inputs;

wherein;

at least one of said respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among said multiple different results based on an output of another one of said respective operator circuits;

said multiple different results comprise sum, sum-plus-1 and sum-plus-2 results; and

one or more of said multiple different results are selectably usable for both fixed-point operations and floating-point operations.

2. The circuitry for performing of claim 1 wherein:

each of said respective operator circuits comprises a fixed-point adder circuit; and

said circuitry for selectively interconnecting comprises control circuitry that receives inputs from two of said respective operator circuits, so that said two of said respective operator circuits provide a floating-point addition of portions of their respective subpluralities of said plurality of inputs.

3. The circuitry for performing of claim 2 further comprising at least one partial product generator;

wherein;

outputs of said at least one partial product generator are input to said two of said respective operator circuits provide a floating-point multiplication of inputs of said at least one partial product generator.

4. The circuitry for performing of claim 1 wherein said circuits for simultaneously computing comprise a half-adder and a prefix network tree.

5. The circuitry for performing of claim 4 wherein:

said prefix network tree comprises first, second and third prefix networks;

said first prefix network receives, as inputs, a first subset of outputs of said half-adder;

said second prefix network receives, as inputs, a second subset of outputs of said half-adder; and

said third prefix network receives, as inputs, outputs of said second prefix network and an output of a most significant node of said first prefix network.

6. The circuitry for performing of claim 5 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is enabled; and

output of said third prefix network is used to provide a combined sum of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder, as well as a combined sum-plus-1 and a combined sum-plus-2.

7. The circuitry for performing of claim 5 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is disabled; and

output of said third prefix network is used to provide separate sums of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder.

8. A specialized processing block on a programmable integrated circuit device, said specialized processing block comprising:

at least one partial product generator providing a plurality of outputs;

at least first and second respective adder circuits, each of said at least first and second respective adder circuits operating on a respective subplurality of said plurality of outputs; and

circuitry for selectively interconnecting said at least first and second respective adder circuits so that they can operate together or separately, according to user selection, on selected ones of (a) said full plurality of outputs, (b) individual ones of said respective subpluralities of said plurality of outputs, or (c) combinations of portions of said respective subpluralities of said plurality of outputs;

wherein;

at least one of said respective adder circuits includes circuits for simultaneously computing multiple different results and for selecting among said multiple different results based on an output of another one of said respective adder circuits; and

said multiple different results comprise sum, sum-plus-1 and sum-plus-2 results.

9. The specialized processing block of claim 8 wherein:

each of said respective adder circuits comprises a fixed-point adder circuit; and

said circuitry for selectively interconnecting comprises control circuitry that receives inputs from two of said respective adder circuits, so that said two of said respective operator circuits provide a floating-point addition of portions of their respective subpluralities of said plurality of outputs.

10. The specialized processing block of claim 8 wherein said circuits for simultaneously computing comprise a half-adder and a prefix network tree.

11. The specialized processing block of claim 10 wherein:

said prefix network tree comprises first, second and third prefix networks;

said first prefix network receives, as inputs, a first subset of outputs of said half-adder;

said second prefix network receives, as inputs, a second subset of outputs of said half-adder; and

said third prefix network receives, as inputs, outputs of said second prefix network and an output of a most significant node of said first prefix network.

12. The specialized processing block of claim 11 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is enabled; and

output of said third prefix network is used to provide a combined sum of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder, as well as a combined sum-plus-1 and a combined sum-plus-2.

13. The specialized processing block of claim 11 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is disabled; and

output of said third prefix network is used to provide separate sums of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder.

14. A programmable integrated circuit device comprising:

a plurality of specialized processing blocks, each of said specialized processing blocks comprising;

at least one partial product generator providing a plurality of outputs;

at least first and second respective adder circuits, each of said at least first and second respective adder circuits operating on a respective subplurality of said plurality of outputs; and

circuitry for selectively interconnecting said at least first and second respective adder circuits so that they can operate together or separately, according to user selection, on selected ones of (a) said full plurality of outputs, (b) individual ones of said respective subpluralities of said plurality of outputs, or (c) combinations of portions of said respective subpluralities of said plurality of outputs;

wherein;

at least one of said respective adder circuits includes circuits for simultaneously computing multiple different results and for selecting among said multiple different results based on an output of another one of said respective adder circuits; and

said multiple different results comprise sum, sum-plus-1 and sum-plus-2 results.

15. The programmable integrated circuit device of claim 14 wherein:

each of said respective adder circuits comprises a fixed-point adder circuit; and

said circuitry for selectively interconnecting comprises control circuitry that receives inputs from two of said respective adder circuits, so that said two of said respective operator circuits provide a floating-point addition of portions of their respective subpluralities of said plurality of outputs.

16. The programmable integrated circuit device of claim 14 wherein said circuits for simultaneously computing comprise a half-adder and a prefix network tree.

17. The programmable integrated circuit device of claim 16 wherein:

said prefix network tree comprises first, second and third prefix networks;

said first prefix network receives, as inputs, a first subset of outputs of said half-adder;

said second prefix network receives, as inputs, a second subset of outputs of said half-adder; and

said third prefix network receives, as inputs, outputs of said second prefix network and an output of a most significant node of said first prefix network.

18. The programmable integrated circuit device of claim 17 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is enabled; and

output of said third prefix network is used to provide a combined sum of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder, as well as a combined sum-plus-1 and a combined sum-plus-2.

19. The programmable integrated circuit device of claim 17 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is disabled; and

output of said third prefix network is used to provide separate sums of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder.