Multi-thread processor and its hardware thread scheduling method

• US 9,098,336 B2
• Filed: 09/14/2012
• Issued: 08/04/2015
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Adachi, Koji, Oomoto, Teppei
• Primary Examiner(s): Kessler, Gregory A
• Application Number:
  US13/619,530
• Publication Number:
  US 20130013900A1
• Time in Patent Office: 1,054 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector. Whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank.

Claims

1. A multi-thread processor comprising:

a plurality of hardware threads each of which generates an independent instruction flow;

a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware thread according to priority rank the priority rank being established in advance for each of the plurality of hardware threads;

a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; and

an execution pipeline that executes an instruction output from the first selector,

wherein if the hardware thread is executed in the execution pipeline, the first scheduler modifies the priority rank for the executed hardware thread and updates the highest priority rank by comparing the modified priority rank with the priority ranks of the other hardware threads;

further comprising a second scheduler that specifies execution of at least one hardware thread selected in a fixed manner among the plurality of hardware threads in a predetermined first execution period, and outputs a second thread selection signal specifying execution of an arbitrary hardware thread in a second execution period other than the first execution period and a real-time bit signal indicating one of the first execution period and the second execution period.

2. A multi-thread processor comprising:

a plurality of hardware threads each of which generates an independent instruction flow;

a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads;

a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; and

an execution pipeline that executes an instruction output from the first selector,

wherein if the hardware thread is executed in the execution pipeline, the first scheduler modifies the priority rank for the executed hardware thread and updates the highest priority rank by comparing the modified priority rank with the priority ranks of the other hardware threads;

further comprising a second selector that receives a real-time bit signal, and when the real-time bit signal indicates the first execution period, provides the second thread selection signal to the first selector, and when the real-time bit signal indicates the second execution period, provides the first thread selection signal to the first selector.

3. A multi-thread processor comprising:

a plurality of hardware threads each of which generates an independent instruction flow;

a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads;

a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; and

an execution pipeline that executes an instruction output from the first selector,

wherein if the hardware thread is executed in the execution pipeline, the first scheduler modifies the priority rank for the executed hardware thread and updates the highest priority rank by comparing the modified priority rank with the priority ranks of the other hardware threads

wherein the hardware threads that are executed in a first execution period are fixed in the first thread scheduler, and

wherein the first selector selects hardware threads by the first thread scheduler in the second execution period to preferentially select hardware threads for which the execution frequency is reduced in the second execution period compared to the first execution period.

4. A multi-thread processor comprising:

a plurality of hardware threads each of which generates an independent instruction flow;

a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads;

a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread; and

an execution pipeline that executes an instruction output from the first selector.,

wherein if the hardware thread is executed in the execution pipeline, the first scheduler modifies the priority rank for the executed hardware thread and updates the highest priority rank by comparing the modified priority rank with the priority ranks of the other hardware threads, and

wherein when a hardware thread that is scheduled to be selected by the first selector cannot be selected due to a state of the execution pipeline, the first thread scheduler recognizes the state of the execution pipeline by a mask signal, and then the first thread scheduler selects a hardware thread other than the hardware thread notified by the mask signal.

5. A hardware thread scheduling method in a multi-thread processor, the multi-thread processor comprising a plurality of hardware threads and being configured to execute an instruction flow generated by the hardware thread while switching the hardware thread in accordance with a predefined schedule, the hardware thread scheduling method comprising:

selecting, according to a first thread selection signal, a hardware thread having a highest priority rank among the plurality of hardware threads;

executing an instruction generated by the selected hardware thread;

updating the priority rank of the hardware thread that generated the executed instruction; and

selecting, according to the first thread selection signal, the hardware thread having a highest priority rank among the updated priority ranks as the hardware thread that generates an instruction next.,

wherein an execution pipeline executes the instruction output,

wherein if the hardware thread is executed in the execution pipeline, the first scheduler modifies the priority rank for the executed hardware thread and updates the highest priority rank by comparing the modified priority rank with the priority ranks of the other hardware threads, and

wherein when a hardware thread that is scheduled to be selected by the first selector cannot be selected due to a state of the execution pipeline, the first thread scheduler recognizes the state of the execution pipeline by a mask signal, and then the first thread scheduler selects a hardware thread other than the hardware thread notified by the mask signal.