PCI express transaction descriptor

• US 9,098,415 B2
• Filed: 11/30/2012
• Issued: 08/04/2015
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David J., Rosenbluth, Mark B., Bhatt, Ajay V., Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert G., Falik, Ohad, Mendelson, Avi, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Martinez, David
• Application Number:
  US13/691,016
• Publication Number:
  US 20130091317A1
• Time in Patent Office: 977 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

an I/O module to;

receive a packet of a transaction over an interconnect from a device, and

identify a hint from a particular header field of the packet, wherein the particular header field is to be included in a transaction descriptor of a header of the packet,

the hint to indicate an intended use of data in a memory associated with the transaction, the header is to comprise at least two bytes, byte zero comprises a first of the at least two bytes, byte one is to be adjacent to byte zero, and the particular header field is to be included in byte one of the header and is to indicate the presence of the hint in the packet.

2. The apparatus of claim 1, wherein the interconnect comprises at least one of a Peripheral Component Interconnect Express (PCIe)-compliant interconnect, a physical layer to support PCIe protocols, a Common Systems Interconnect (CSI)-compliant interconnect, and a physical layer to support a layered communication protocol.

3. The apparatus of claim 1, wherein the apparatus comprises a root controller and the I/O module is included in the root controller.

4. The apparatus of claim 3, wherein the root controller is configured to perform an action on the memory based at least in part on the hint.

5. The apparatus of claim 4, wherein the action is included in completion of the transaction.

6. The apparatus of claim 1, wherein the transaction includes a read request of the memory.

7. The apparatus of claim 1, wherein the transaction includes a write request of the memory.

8. The apparatus of claim 1, wherein the transaction includes a request to read and write to the memory.

9. The apparatus of claim 1, wherein the packet includes the header and a data payload.

10. The apparatus of claim 1, wherein the header is a transaction layer header and includes the hint.

11. The apparatus of claim 1, wherein the memory is identifiable from the hint.

12. The apparatus of claim 1, wherein the memory is cache data.

13. The apparatus of claim 1, wherein the hint is included in a first request and the intended use comprises a potential use of the data in connection with a second subsequent request.

14. An apparatus comprising:

an I/O module to;

insert a hint into at least one packet of a transaction, wherein the packet is to comprise a header, the header is to comprise at least two bytes, the hint is identifiable from a value of a particular header field in a transaction descriptor to the included in the header of the packet, byte zero is a first of the at least two bytes, byte one is a second of the at least two bytes, byte one is adjacent to byte zero, the particular field is to be included in byte one of the header, and the hint is to indicate an intended use of data in a memory associated with the transaction; and

send the packet to a device over an interconnect.

15. The apparatus of claim 14, wherein the interconnect comprises at least one of a Peripheral Component Interconnect Express (PCIe)-compliant interconnect, a physical layer to support PCIe protocols, a Common Systems Interconnect (CSI)-compliant interconnect, and a physical layer to support a layered communication protocol.

16. The apparatus of claim 14, wherein the hint is included in the header of the packet.

17. The apparatus of claim 14, wherein the packet is associated with a request of the memory.

18. The apparatus of claim 17, wherein the request is one of a group comprising:

a) a read request of the memory;

b) a write request of the memory; and

c) a read and write request of the memory.

19. An apparatus comprising:

a root controller including an I/O module configured to receive a packet from a device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect, wherein the I/O module is to include a protocol stack including a transaction layer, a link layer, and a physical layer, the packet is to include a transaction layer header and a data payload, the transaction layer header is to include a transaction descriptor, the transaction layer header is to comprise at least two bytes, byte zero comprises a first of the at least two bytes, byte one is to be adjacent to byte zero, the transaction descriptor is to include one or more attribute fields, and a particular one of the attribute fields is to identify a hint and is to be included in byte one of the transaction layer header,

wherein the packet is associated with a request of cache data and the hint is to indicate an intended use of the cache data and the cache data is to be identifiable from the hint.

20. A method comprising:

defining a hint for a transaction;

generating a packet to include a header with a transaction descriptor including a plurality of attribute fields, wherein the header comprises at least two bytes, byte zero comprises a first of the at least two bytes, byte one is adjacent to byte zero, a particular attribute field of the transaction descriptor identifies the hint, and the particular attribute field is included in byte one; and

sending the packet in the transaction using a Peripheral Component Interconnect Express (PCIe)-compliant interconnect, wherein the transaction includes a request of a memory;

wherein the hint indicates an intended use of the memory.

21. The method of claim 20, further comprising performing the intended use in association with the transaction.

22. The method of claim 20, wherein the intended use is not performed.

23. The method of claim 20, wherein the hint is included in the header of the packet included in the transaction.

24. The method of claim 23, wherein the header is a transaction layer header.

25. The method of claim 20, wherein the memory includes cache data and the intended use corresponds to the cache data.

26. The method of claim 20, wherein the request is one of a group comprising:

a) a read request of the memory space;

b) a write request of the memory space; and

c) a read and write request of the memory space.

27. A system comprising:

a first device;

a second device to;

receive a transaction request from the first device using a Peripheral Component Interconnect Express (PCIe)-compliant interconnect, wherein the interconnect includes a transaction layer and the transaction request includes a request of a memory; and

identify a hint from a particular field of a transaction descriptor of a header included in the transaction request, wherein the header is to comprise at least two bytes, byte zero comprises a first of the at least two bytes, byte one is to be adjacent to byte zero, the hint is to indicate an intended use of the memory by the first device, and the particular field is to be included in byte one of the header.

28. The system of claim 27, wherein the second device is further configured to perform an action on the memory based at least in part on the hint.

29. The system of claim 27, wherein the first device is communicatively coupled to the second device using the interconnect.

30. The system of claim 27, wherein the memory includes cache data.

31. The system of claim 27, wherein the first device includes a first microcontroller device and the second device includes a second microcontroller device.

32. An apparatus comprising:

logic to;

receive a packet, wherein the packet comprises a header, the header is to include a transaction descriptor that is to include a transaction identifier and a hint field, the header is to comprise at least two bytes, byte zero comprises a first of the at least two bytes, byte one is to be adjacent to byte zero, the packet is to be received over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect and the hint field is to be included in byte one of the header; and

service the packet to identify an intended use of a memory based at least in part on a value of the hint field.

33. The apparatus of claim 32, wherein the value of the hint field indicates the presence of a hint included in the packet, wherein the hint identifies the intended use.

34. The apparatus of claim 32, wherein the header comprises a transaction layer header of the packet.

35. The apparatus of claim 32, wherein the transaction descriptor includes at least one attribute field and the attribute field includes at least one of a group comprising:

a) a priority field;

b) an ordering field; and

c) a no-snoop field.

36. An apparatus comprising:

logic to;

generate a packet to include a header, wherein the header is to include a transaction descriptor that is to include a transaction identifier and a hint field, the header is to comprise at least two bytes, byte zero comprises a first of the at least two bytes, byte one is to be adjacent to byte zero, the hint field is to be included in byte one of the header and is to indicate the presence of a hint included in the packet, the hint is to identify an intended use of a memory based at least in part on a value of the hint field; and

send the packet to a device over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect.

37. The apparatus of claim 36, wherein the device includes the memory.

38. The apparatus of claim 36, wherein the header comprises a transaction layer header of the packet.

39. The apparatus of claim 36, wherein the transaction descriptor includes at least one attribute field and the attribute field includes at least one of a group comprising:

a) a priority field;

b) an ordering field; and

c) a no-snoop field.