Clock distribution network for 3D integrated circuit

• US 9,098,666 B2
• Filed: 03/11/2013
• Issued: 08/04/2015
• Est. Priority Date: 11/28/2012
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Samadi, Kambiz, Panth, Shreepad A., Xie, Jing, Du, Yang
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/792,486
• Publication Number:
  US 20140145347A1
• Time in Patent Office: 876 Days
• Field of Search: 716/100, 716/104, 716/110, 716/114, 716118-120, 716/136, 716/130, 716/132, 716/134
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Claims

1. A non-transitory computer readable medium having instructions stored thereon that when executed by a computer performs a method of developing a clock distribution network for an integrated circuit, the method comprising:

capturing sources of clock skew including timing mismatches between clock sinks;

moving the clock sinks to a clock distribution network;

synthesizing a behavioral description of the integrated circuit and said sources of clock skew to generate a 2D layout comprising the clock distribution network and combinational logic;

separating said clock distribution network from said combinational logic and locating said clock distribution network to a first area of the integrated circuit;

determining vias to provide via connections between the clock distribution network and the combinational logic, where the via connections are where the clock sinks were located before the step of moving the clock sinks; and

floorplanning said combinational logic of said first area.

2. The non-transitory computer readable medium of claim 1, the method further comprising the step of applying further optimization to said clock distribution network of said first area.

3. The non-transitory computer readable medium of claim 2, the method wherein said further optimization comprises clock tree synthesis.

4. The non-transitory computer readable medium of claim 3, the method wherein said further optimization comprises block-level routing.

5. The non-transitory computer readable medium of claim 4, the method wherein said further optimization comprises post-route optimization.

6. The non-transitory computer readable medium of claim 2, the method wherein:

the integrated circuit comprises a multi-tier circuit;

said first area comprises a first tier of said multi-tier circuit; and

said combinational logic is located to a second tier of said multi-tier circuit.

7. The non-transitory computer readable medium of claim 6, the method wherein said first tier is adjacent said second tier.

8. The non-transitory computer readable medium of claim 6, the method wherein:

said combinational logic further comprises non-timing critical combinational logic; and

said non-timing critical combinational logic is located to a third tier of said multi-tier circuit.

9. The non-transitory computer readable medium of claim 8, wherein said third tier is not adjacent said first tier.

10. The non-transitory computer readable medium of claim 6, the method wherein:

said timing-critical combinational logic is further located to a fourth tier of said multi-tier circuit; and

said fourth tier is adjacent said first tier.

11. The non-transitory computer readable medium of claim 10, the method wherein:

said combinational logic comprises further non-timing critical combinational logic; and

said non-timing critical combinational logic is located to a fifth tier of said multi-tier circuit.

12. The non-transitory computer readable medium of claim 11, the method wherein said fifth tier is not adjacent said first tier.

13. The non-transitory computer readable medium of claim 1, the method wherein said vias comprise inter-tier vias.

14. The non-transitory computer readable medium of claim 13, the method wherein said inter-tier vias comprise high-density.

15. The non-transitory computer readable medium of claim 1, the integrated circuit comprising:

the clock distribution network separated to a first tier of said integrated circuit; and

the combinational logic separated to a second tier of said integrated circuit;

wherein the vias connect said first tier to said second tier.

16. The non-transitory computer readable medium of claim 15 wherein:

the integrated circuit comprises a multi-tier circuit.

17. The non-transitory computer readable medium of claim 16 wherein said first tier is adjacent said second tier.

18. The non-transitory computer readable medium of claim 16 wherein:

said integrated circuit further comprises non-timing critical combinational logic;

said non-timing critical combinational logic is separated to a third tier of said integrated circuit.

19. The non-transitory computer readable medium of claim 18 wherein said third tier is not adjacent said first tier.

20. The non-transitory computer readable medium of claim 16 wherein:

said combinational logic is further located to a fourth tier of said multi-tier circuit; and

said fourth tier is adjacent said first tier.

21. The non-transitory computer readable medium of claim 20 wherein:

said integrated circuit further comprises non-timing critical combinational logic; and

said non-timing critical combinational logic is located to a fifth tier of said multi-tier circuit.

22. The non-transitory computer readable medium of claim 21 wherein said fifth tier is not adjacent said first tier.

23. The non-transitory computer readable medium of claim 15 wherein said vias comprise inter-tier vias.

24. The non-transitory computer readable medium of claim 23 wherein said inter-tier vias comprise high-density vias.