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Systems and methods for detecting attacks against a digital circuit

  • US 9,098,700 B2
  • Filed: 02/28/2011
  • Issued: 08/04/2015
  • Est. Priority Date: 03/01/2010
  • Status: Active Grant
First Claim
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1. A system for detecting attacks against a hardware-implemented circuit, the hardware-implemented circuit comprising functional units, the system comprising:

  • a micro-architectural target unit selected from among the functional units of the hardware-implemented circuit for monitoring;

    a micro-architectural predictor unit, selected from among the functional units of the hardware-implemented circuit, configured to output predicted event messages representative of predicted micro-architectural output produced by the target unit in response to micro-architectural input provided by the predictor unit to the target unit;

    a micro-architectural reactor unit selected from among the functional units of the hardware-implemented circuit arranged to receive actual micro-architectural output caused by the target unit in response to the micro-architectural input provided by the predictor unit to the target unit, the reactor unit further configured to output actual event messages representative of the actual micro-architectural output caused by the target unit in response to the micro-architectural input provided by the predictor unit to the target unit; and

    a micro-architectural monitor unit arranged to receive the predicted event messages from the predictor unit and the actual event messages from the reactor unit;

    wherein the monitor unit is configured to indicate an alarm based on a comparison of the predicted event messages received from the predictor unit and the actual event messages received from the reactor unit; and

    wherein the predicted event messages each comprise one of;

    i) a predicted event bit generated by the predictor unit for each micro-architectural transaction predicted to be caused by the target unit in response to the micro-architectural input provided by the predictor unit to the target unit, and wherein, when the predicted event messages each comprise a respective predicted event bit, the actual event messages each comprise an actual event bit generated by the reactor unit for each actual micro-architectural transaction caused by the target unit in response to the micro-architectural input provided by the predictor unit to the target unit, and wherein a bit total discrepancy between a predicted number of bits predicted by the predictor unit and an actual number of bits generated by the reactor unit is indicative of an emitter backdoor implementation in the target unit;

    or ii) a predicted event value generated by the predictor unit representative of a predicted instruction type for a predicted instruction provided by the target unit to the reactor unit in response to the micro-architectural input provided by the predictor unit to the target unit, and wherein, when the predicted event message each comprise a respective predicted event value, the actual event messages each comprise an actual event value generated by the reactor unit representative of an actual instruction type for an actual instruction provided by the target unit to the reactor unit in response to the micro-architectural input provided by the predictor unit to the target unit, and wherein an instruction type value discrepancy between the predicted event value generated by the predictor unit and the actual event value generated by the reactor unit is indicative of a corruptor backdoor implementation in the target unit.

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