Using different programming modes to store data to a memory cell

• US 9,099,185 B2
• Filed: 12/20/2013
• Issued: 08/04/2015
• Est. Priority Date: 12/20/2013
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Kim, YoungPil, Bowman, Rodney Virgil, Setiadi, Dadi, Tian, Wei
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/136,708
• Publication Number:
  US 20150179268A1
• Time in Patent Office: 592 Days
• Field of Search: 365/148, 365/185.03, 365/236
• US Class Current: 1/1
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a memory cell is provided with a plurality of available programming states to accommodate multi-level cell (MLC) programming. A control circuit stores a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states. The control circuit subsequently stores a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.

Claims

1. An apparatus comprising:

a memory cell having a plurality of available programming states to accommodate multi-level cell (MLC) programming; and

a control circuit which stores only a single bit logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states, and which subsequently stores only a single bit logical value to the memory cell using virtual multi-level cell (VMLC) programming to provide a larger, second read margin between the first available programming state and a third available programming state.

2. The apparatus of claim 1, wherein the control circuit erases the memory cell between the storage of the single bit logical value using SLC programming and the storage of the single bit logical value using VMLC programming.

3. The apparatus of claim 1, wherein the memory cell is a flash memory cell and each of the plurality of available programming states corresponds to a different total amount of accumulated charge on a floating gate of the flash memory cell.

4. The apparatus of claim 1, wherein the memory cell is a resistive sense memory (RSM) cell and each of the plurality of available programming states corresponds to a different programmed electrical resistance of the cell.

5. The apparatus of claim 1, wherein the first available programming state corresponds to substantially no accumulated charge on a floating gate of the memory cell, the second available programming state corresponds to an intermediate amount of accumulated charge on the floating gate, and the third available programming state corresponds to a maximum amount of accumulated charge on the floating gate.

6. The apparatus of claim 1, wherein the control circuit applies a first read voltage threshold to the memory cell which falls within the first read margin to identify the single bit logical value stored using SLC programming, and applies a different, second read voltage threshold to the memory cell which falls within the second read margin to identify the single bit logical value stored using VMLC programming.

7. The apparatus of claim 1, wherein the control circuit is further configured to use MLC programming to store a multi-bit logical value to the memory cell from available programming states that sequentially correspond to first, second, third and fourth multi-bit logical values, wherein the first available programming state used during SLC and VMLC programming corresponds to the available programming state used during MLC programming to represent the first multi-bit logical value, and the third available programming state used during VMLC programming corresponds to the available programming state used during MLC programming to represent the fourth multi-bit logical value.

8. The apparatus of claim 7, wherein the first, second, third and fourth multi-bit logical values are 11, 01, 00 and 10, respectively.

9. The apparatus of claim 1, wherein the control circuit switches from programming the memory cell using SLC programming to programming the memory cell using VMLC programming responsive to an accumulated aging parameter.

10. The apparatus of claim 9, wherein the accumulated aging parameter comprises a total accumulated count of program/erase (PE) cycles applied to the memory cell, and wherein the control circuit switches from SLC programming to VMLC programming responsive to the accumulated count of PE cycles reaching a predetermined threshold.

11. The apparatus of claim 1, wherein the control circuit programs the memory cell using MLC programming during a first number of consecutive program/erase (PE) cycles upon the memory cell, the control circuit programs the memory cell using SLC programming during a subsequent second number of consecutive PE cycles upon the memory cell, and the control circuit programs the memory cell using VMLC programming during a subsequent third number of consecutive PE cycles upon the memory cell.

12. An apparatus comprising:

a memory cell having sequential first, second, third and fourth available programming states to accommodate the storage of one or more bits to the memory cell, each bit having an associated logical value; and

a control circuit adapted to alternately store a single bit to the memory cell using single level cell (SLC) programming, multiple bits to the memory cell using multi-level cell (MLC) programming, and a single bit to the memory cell using virtual multi-level cell (VMLC) programming, wherein the SLC programming uses the first and third available programming states to alternately indicate the associated logical value of the stored single bit, wherein the MLC programming uses the first, second, third and fourth available programming states to alternately indicate the associated logical values of the stored multiple bits, and the VMLC programming uses the first and fourth available programming states to alternately indicate the associated logical value of the stored single bit.

13. The apparatus of claim 12, wherein the control circuit erases the memory cell between the storage of the single bit logical value using SLC programming and the storage of the single bit logical value using VMLC programming.

14. The apparatus of claim 12, wherein the memory cell is a flash memory cell and the first, second, third and fourth available programming states correspond to different total amounts of accumulated charge on a floating gate of the flash memory cell.

15. The apparatus of claim 12, wherein the memory cell is a resistive sense memory (RSM) cell and each of the plurality of available programming states corresponds to a different programmed electrical resistance of the cell.

16. The apparatus of claim 12, wherein the control circuit switches from using SLC or MLC programming to program the memory cell to using VMLC programming to program the memory cell responsive to a parameter associated with the memory cell.

17. The apparatus of claim 16, wherein the parameter comprises a total accumulated count of program/erase (PE) cycles applied to the memory cell, and wherein the control circuit switches from SLC or MLC programming to VMLC programming responsive to the accumulated count of PE cycles reaching a predetermined threshold.

18. The apparatus of claim 12, wherein the control circuit programs the memory cell using MLC programming during a first number of consecutive program/erase (PE) cycles upon the memory cell, the control circuit programs the memory cell using SLC programming during a subsequent second number of consecutive PE cycles upon the memory cell, and the control circuit programs the memory cell using VMLC programming during a subsequent third number of consecutive PE cycles upon the memory cell.

19. A method comprising:

providing a memory cell having a plurality of available programming states to accommodate the storage of one or more bits to the memory cell, each bit having an associated logical value;

storing a single bit having an associated logical value to the memory cell using single level cell (SLC) programming to provide a first read margin between first and second available programming states of said plurality; and

storing a single bit having an associated logical value to the memory cell using virtual multi-level cell (VMLC) programming having a larger, second read margin between the first available programming state and a third available programming state of said plurality.

20. The method of claim 19, further comprising erasing the memory cell between the respective storing steps, and storing the single bit using VMLC programming responsive to an accumulated aging parameter associated with the memory cell reaching a predetermined threshold.