Memory component with pattern register circuitry to provide data patterns for calibration

• US 9,099,194 B2
• Filed: 08/14/2013
• Issued: 08/04/2015
• Est. Priority Date: 10/22/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Hampel, Craig E., Perego, Richard E., Sidiropoulos, Stefanos, Tsern, Ely K., Ware, Frederick A.
• Primary Examiner(s): Puente, Eva
• Application Number:
  US13/967,245
• Publication Number:
  US 20130346685A1
• Time in Patent Office: 720 Days
• Field of Search: 365/193, 365/194, 365/222, 365/233.1
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 21/00 Digital stores in which the information circulates continuouslystepwise G11C19/00
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 7/0025 : interpolation of clock signal
• CPC Class Codes: H04L 7/0079 : Receiver details
• CPC Class Codes: H04L 7/0091 : Transmitter details
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Claims

1. A memory component comprising;

a memory core;

a first circuit to receive external commands, the external commands including a read command that specifies transmitting data accessed from the memory core, and a write command that specifies storing data, provided to the memory component, in the memory core;

a second circuit to transmit data onto an external bus in response to a read command;

pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern, wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration, wherein the pattern register circuitry includes at least first and second data pattern registers to provide the first and second data patterns, respectively, wherein at least one of the first and second data pattern registers is loaded with at least one of the first and second data patterns in response to a write command received during the calibration; and

an input to receive a reset signal, wherein the first and second data pattern registers are set to be predefined values upon receipt of the reset signal.

2. The memory component of claim 1, wherein the read command received during the calibration selects the one of the first and second data patterns to be transmitted by the second circuit onto the external bus.

3. The memory component of claim 1, wherein the write command received during the calibration selects the at least one of the first and second data pattern registers to be loaded with the at least one of the first and second data patterns.

4. The memory component of claim 1, wherein:

the first data pattern register is associated with a first pattern-selection signal;

the second data pattern register is associated with a second pattern-selection signal that is different from the first pattern-selection signal;

the first data pattern is selected to be transmitted by the second circuit onto the external bus when the read command received during the calibration includes the first pattern-selection signal; and

the second data pattern is selected to be transmitted by the second circuit onto the external bus when the read command received during the calibration includes the second pattern-selection signal.

5. The memory component of claim 1, including multiplexer circuitry that allows data to be routed either:

from the memory core to the second circuit;

or

from at least one of the first and second data pattern registers to the second circuit.

6. The memory component of claim 1, wherein the memory component is configured to:

calibrate a read timing value associated with the memory component after the first data pattern register and the second data pattern register are set to the predefined values; and

calibrate a write timing value associated with the memory component after at least one of the first data pattern register and the second data pattern register is loaded with a data pattern received during the calibration.

7. The memory component of claim 1, wherein the reset signal is a sideband signal.

8. A method of operation in a memory component having a memory core, the method comprising;

receiving external commands, the external commands including a read command and a write command;

storing data, provided to the memory component, in the memory core, in response to the write command;

transmitting onto an external bus, data accessed from the memory core, in response to the read command;

receiving a reset signal;

setting first and second data pattern registers to be predefined values in response to receiving the reset signal; and

during calibration;

loading at least one of the first and second data pattern registers with at least one of first and second data patterns, in response to a write command received during the calibration; and

transmitting onto the external bus, a selected one of the first and second data patterns, in response to a read command received during the calibration.

9. The method of claim 8, wherein the read command received during the calibration selects the one of the first and second data patterns to be transmitted by the second circuit onto the external bus.

10. The method of claim 8, wherein the write command received during the calibration selects the at least one of the first and second data pattern registers to be loaded with the at least one of the first and second data patterns.

11. The method of claim 8, wherein:

the first data pattern register is associated with a first pattern-selection signal;

the second data pattern register is associated with a second pattern-selection signal that is different from the first pattern-selection signal;

when the read command received during the calibration includes the first pattern-selection signal, transmitting the first data pattern onto the external bus via the second circuit; and

when the read command received during the calibration includes the second pattern-selection signal, transmitting the second data pattern onto the external bus via the second circuit.

12. The method of claim 8, including:

routing data from the memory core to the second circuit through a multiplexer;

changing a select setting of the multiplexer; and

after changing the select setting of the multiplexer, routing data from one of the first and second data pattern registers to the second circuit through the multiplexer.

13. The method of claim 8, including:

calibrating a read timing value associated with the memory component after the first data pattern register and the second data pattern register are set to the predefined values; and

calibrating a write timing value associated with the memory component using pattern data loaded in at least one of the first data pattern register and the second data pattern register during the calibration.

14. The method of claim 8, wherein the reset signal is a sideband signal.

15. A memory component comprising:

a memory core;

pattern register circuitry to provide a first calibration data pattern that is associated with a first pattern-selection signal and a second calibration data pattern that is associated with a second pattern-selection signal different from the first pattern-selection signal;

a command interface to receive commands from a memory controller, the commands including a read command and a write command; and

a data interface coupled to the pattern register circuitry and the memory core, wherein;

when the command interface receives a read command during normal operation, the data interface outputs data accessed from the memory core;

when the command interface receives a read command during calibration the data interface outputs data that was stored as one of the first and second calibration data patterns; and

when the command interface receives a write command during calibration the data interface receives data, comprising at least one of the first calibration data pattern and the second calibration data pattern, to be loaded in the pattern register circuitry.

16. The memory component of claim 15, wherein:

the pattern register circuitry includes;

a first portion that is associated with the first pattern-selection signal; and

a second portion that is associated with the second pattern-selection signal; and

the memory component includes a respective interface coupled to the pattern registry circuitry for;

replacing a first predefined value stored in a first portion of the pattern registry circuitry with a first externally-specified value; and

replacing a second predefined value stored in a second portion of the pattern registry circuitry with a second externally-specified value.

17. The memory component of claim 15, wherein

when the respective read command is received during calibration and includes the first pattern-selection signal, the respective data includes a value stored as the first calibration data pattern;

and

when the respective read command is received during calibration and includes the second pattern-selection signal, the respective data includes a value stored as the second calibration data pattern.

18. The memory component of claim 15, wherein the memory component is configured to:

calibrate a read timing value associated with the memory component after the first calibration data pattern and the second calibration data pattern are set to predefined values; and

calibrate a write timing value associated with the memory component using pattern data loaded in the pattern register circuitry during the calibration.

19. The memory component of claim 15, including an input to receive a reset signal, wherein the first calibration data pattern associated with the first pattern-selection signal and a second calibration data pattern associated with the second pattern-selection signal are set to be predefined values upon receipt of the reset signal.

20. The memory component of claim 15, wherein the write command to load the pattern register circuitry with an externally-specified value is a sideband signal.