Three-dimensional semiconductor memory devices and method of fabricating the same
First Claim
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1. A three-dimensional semiconductor memory device, comprising:
- an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, at least an uppermost electrode of the electrodes being divided into a plurality of physically isolated segments arranged in the first direction;
vertical active patterns that penetrate the electrode structure; and
an electrode-dielectric layer disposed between each of the vertical, active patterns and each of the electrodes,wherein the segments of the uppermost electrode are electrically connected to each other.
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Abstract
Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other.
28 Citations
15 Claims
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1. A three-dimensional semiconductor memory device, comprising:
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an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, at least an uppermost electrode of the electrodes being divided into a plurality of physically isolated segments arranged in the first direction; vertical active patterns that penetrate the electrode structure; and an electrode-dielectric layer disposed between each of the vertical, active patterns and each of the electrodes, wherein the segments of the uppermost electrode are electrically connected to each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 15)
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11. A three-dimensional semiconductor memory device, comprising:
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a substrate; an electrode structure on the substrate, the electrode structure extending in a horizontal direction and including a plurality of electrode layers and a plurality of insulating pattern layers that are stacked in an alternating manner on the substrate in a vertical direction, wherein at least an uppermost electrode layer of the electrode structure is divided into first and second horizontal segments arranged in the horizontal direction, wherein at least a lowermost electrode layer of the electrode structure extends from a region below the first horizontal segment toward another region below the second horizontal segment; a plurality of vertical active patterns that extend through the electrode structure in the vertical direction; and a plurality of dielectric layers between the vertical active patterns and respective ones of the electrode layers; wherein the first and second horizontal segments of the uppermost electrode are electrically connected to each other. - View Dependent Claims (13)
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14. A three-dimensional semiconductor memory device, comprising:
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a substrate; an electrode structure on the substrate, the electrode structure including a plurality of electrode layers and a plurality of insulating pattern layers that are stacked in an alternating manner on the substrate in a vertical direction, wherein at least an uppermost electrode layer of the electrode structure is divided into first and second horizontal segments and wherein a lowermost electrode layer is not divided into horizontal segments; a plurality of vertical active patterns that extend through the electrode structure in the vertical direction including a first vertical active pattern that penetrates the first horizontal segment of the uppermost electrode and a second vertical active pattern that penetrates the second horizontal segment of the uppermost electrode; a plurality of dielectric layers separating the vertical active patterns and respective ones of the electrode layers; and a plurality of bit lines coupled to respective ones of the plurality of vertical active patterns; wherein the first and second horizontal segments of the uppermost electrode are electrically connected to each other.
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Specification