Test method and test arrangement

• US 9,099,419 B2
• Filed: 10/09/2012
• Issued: 08/04/2015
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Hirler, Franz, Nelle, Peter
• Primary Examiner(s): Hollington, Jermele M
• Application Number:
  US13/647,480
• Publication Number:
  US 20140097863A1
• Time in Patent Office: 1,029 Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Claims

1. A test method, comprising:

providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controlled from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell,

wherein a potential of the at least one additional electrode is electrically insulated from potentials of each of the at least one first terminal electrode region, the at least one second terminal electrode region, and the at least one gate electrode.

2. The method of claim 1,

wherein the semiconductor device is configured as a transistor.

3. The method of claim 1,

wherein the at least one gate electrode is disposed at least partially in the at least one trench.

4. The method of claim 1,

wherein the at least one additional electrode is configured as a shield electrode.

5. The method of claim 1,

wherein the at least one test potential is configured to detect one or more defects in the at least one trench.

6. The method of claim 1,

wherein the at least one cell comprises at least one contact trench, and wherein the at least one test potential is configured to detect one or more defects in the at least one contact trench.

7. The method of claim 1,

wherein the at least one test potential is configured to determine a breakdown voltage of the semiconductor device.

8. The method of claim 1,

wherein applying at least one test potential to at least the at least one additional electrode comprises forcing a predeterminable electrical current through the semiconductor device.

9. The method of claim 1,

wherein applying at least one test potential to at least the at least one additional electrode comprises applying a plurality of test potentials to the at least one additional electrode, and

wherein the method further comprises:

measuring a breakdown voltage of the semiconductor device for each of the plurality of test potentials.

10. The method of claim 1,

wherein the at least one test potential is configured to determine a strength of an insulating layer in the at least one trench.

11. The method of claim 1,

wherein the at least one additional electrode is insulated by an insulating layer disposed in the at least one trench,

wherein applying at least one test potential to at least the at least one additional electrode comprises applying a plurality of test potentials to the at least one additional electrode, and

wherein the method further comprises:

measuring a tunnel current through the insulating layer for each of the plurality of test potentials.

12. The method of claim 1,

wherein at least one of the at least one gate electrode and the at least one additional electrode comprises polysilicon.

13. The method of claim 1,

wherein the semiconductor device comprises a plurality of device cells electrically connected in parallel, each device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode,

wherein the at least one test potential is applied to all device cells of the plurality of device cells simultaneously.

14. The method of claim 1,

wherein applying the at least one test potential to at least the at least one additional electrode comprises using a plurality of probes.

15. The method of claim 1,

wherein applying the at least one test potential to at least the at least one additional electrode is carried out in a front end processing stage of the semiconductor device.

16. A test arrangement, comprising:

a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region, at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

a test device configured to apply at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell,

wherein a potential of the at least one additional electrode is electrically insulated from potentials of each of the at least one first terminal electrode region, the at least one second terminal electrode region, and the at least one gate electrode.

17. A test method, comprising:

providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controlled from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell,

wherein applying at least one test potential to at least the at least one additional electrode comprises carrying out an avalanche test.

18. The method of claim 17,

wherein the avalanche test comprises applying one or more avalanche pulses to the semiconductor device.

19. A test method, comprising:

providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controlled from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell,

wherein applying the at least one test potential comprises subjecting the semiconductor device to at least one of a defect density scan and a reliability scan.

20. A test method, comprising:

providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controlled from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell, and

analyzing test results obtained by applying the at least one test potential, by means of dynamical part average testing (PAT).

21. A test method, comprising:

providing a semiconductor device to be tested, the semiconductor device comprising at least one device cell, the at least one device cell comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controlled from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell,

wherein the semiconductor device is formed in a semiconductor workpiece, the workpiece comprising a plurality of pads including at least a first pad coupled to the at least one first terminal electrode region, a second pad coupled to the at least one second terminal electrode region, a third pad coupled to the at least one gate electrode and a fourth pad coupled to the at least one additional electrode, and

wherein the fourth pad coupled to the at least one additional electrode is electrically insulated from the first to third pads.

22. The method of claim 21, further comprising:

electrically connecting the fourth pad to at least one of the first to third pads after applying the at least one test potential to at least the at least one additional electrode.

23. The method of claim 22, further comprising:

wherein electrically connecting the fourth pad to at least one of the first to third pads is carried out in a back end processing stage of the semiconductor device.