Semiconductor device and method for manufacturing the same

• US 9,099,498 B2
• Filed: 07/03/2014
• Issued: 08/04/2015
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/323,401
• Publication Number:
  US 20140315349A1
• Time in Patent Office: 397 Days
• Field of Search: 438/85, 438/86, 438/104, 438/482, 438/754, 257/43, 257/52, 257/E21.46, 257/E21.409
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/426 using masks
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor film over a substrate during heat treatment to the substrate;

forming a gate insulating film over the oxide semiconductor film;

forming a first electrode over the gate insulating film;

forming a first sidewall insulating film and a second sidewall insulating film on side surfaces of the first electrode; and

adding a dopant to the oxide semiconductor film to form a first region, a pair of second regions and a pair of third regions of the oxide semiconductor film,

wherein the first electrode overlaps with the first region,

wherein the first sidewall insulating film overlaps with one of the pair of second regions, and the second sidewall insulating film overlaps with the other of the pair of second regions,

wherein the first region and the pair of second regions are located between the pair of third regions,

wherein the first region is a c-axis aligned crystalline oxide semiconductor region,

wherein each of a crystallinity of the pair of second regions and a crystallinity of the pair of third regions is lower than a crystallinity of the first region, and

wherein a dopant concentration of the pair of third regions is higher than a dopant concentration of the pair of second regions.

2. The method for manufacturing a semiconductor device according to claim 1,

wherein the gate insulating film is an oxide insulating film, and

wherein each of the first sidewall insulating film and the second sidewall insulating film is a nitride insulating film.

3. The method for manufacturing a semiconductor device according to claim 1,

wherein each of the gate insulating film, the first sidewall insulating film and the second sidewall insulating film is an oxide insulating film.

4. The method for manufacturing a semiconductor device according to claim 1,

wherein the pair of second regions and the pair of third regions comprise one or more elements selected from nitrogen, phosphorus, and arsenic as the dopant, and

wherein the dopant concentration of the pair of second regions and the dopant concentration of the pair of third regions are higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

5. The method for manufacturing a semiconductor device according to claim 1,

wherein the pair of second regions and the pair of third regions comprise one or more elements selected from nitrogen, phosphorus, and arsenic as the dopant,

wherein the dopant concentration of the pair of second regions is higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than 5×

10¹⁹ atoms/cm³, and

wherein the dopant concentration of the pair of third regions is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

6. The method for manufacturing a semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises two or more elements selected from In, Ga, Sn, and Zn.

17. The method for manufacturing a semiconductor device according to claim 1, wherein each of the first sidewall insulating film and the second sidewall insulating film is on side surfaces of the gate insulating film.

7. A method for manufacturing a semiconductor device comprising the steps of:

forming a first oxide semiconductor film over a substrate;

performing first heat treatment to form a first crystalline oxide semiconductor film after forming the first oxide semiconductor film;

forming a second oxide semiconductor film over the first crystalline oxide semiconductor film;

performing second heat treatment to form a second crystalline oxide semiconductor film after forming the second oxide semiconductor film;

forming a gate insulating film over an oxide semiconductor film that comprises the first crystalline oxide semiconductor film and the second crystalline oxide semiconductor film;

forming a first electrode over the gate insulating film;

forming a first sidewall insulating film and a second sidewall insulating film on side surfaces of the first electrode; and

adding a dopant to the oxide semiconductor film to form a first region, a pair of second regions and a pair of third regions of the oxide semiconductor film,

wherein the first electrode overlaps with the first region,

wherein the first sidewall insulating film overlaps with one of the pair of second regions, and the second sidewall insulating film overlaps with the other of the pair of second regions,

wherein the first region and the pair of second regions are located between the pair of third regions,

wherein the first region is a c-axis aligned crystalline oxide semiconductor region,

wherein each of a crystallinity of the pair of second regions and a crystallinity of the pair of third regions is lower than a crystallinity of the first region, and

wherein a dopant concentration of the pair of third regions is higher than a dopant concentration of the pair of second regions.

8. The method for manufacturing a semiconductor device according to claim 7,

wherein the gate insulating film is an oxide insulating film, and

wherein each of the first sidewall insulating film and the second sidewall insulating film is a nitride insulating film.

9. The method for manufacturing a semiconductor device according to claim 7,

wherein each of the gate insulating film, the first sidewall insulating film and the second sidewall insulating film is an oxide insulating film.

10. The method for manufacturing a semiconductor device according to claim 7,

wherein the pair of second regions and the pair of third regions comprise one or more elements selected from nitrogen, phosphorus, and arsenic as the dopant, and

wherein the dopant concentration of the pair of second regions and the dopant concentration of the pair of third regions are higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

11. The method for manufacturing a semiconductor device according to claim 7,

wherein the pair of second regions and the pair of third regions comprise one or more elements selected from nitrogen, phosphorus, and arsenic as the dopant,

wherein the dopant concentration of the pair of second regions is higher than or equal to 5×

10¹⁸ atoms/cm³ and lower than 5×

10¹⁹ atoms/cm³, and

wherein the dopant concentration of the pair of third regions is higher than or equal to 5×

10¹⁹ atoms/cm³ and lower than or equal to 1×

10²² atoms/cm³.

12. The method for manufacturing a semiconductor device according to claim 7,

wherein the oxide semiconductor film comprises two or more elements selected from In, Ga, Sn, and Zn.

13. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating film on a substrate in an atmosphere gas containing oxygen;

forming a first oxide semiconductor film on the insulating film;

performing first heat treatment to form a first crystalline oxide semiconductor film after forming the first oxide semiconductor film;

forming a second oxide semiconductor film over the first crystalline oxide semiconductor film;

performing second heat treatment to form a second crystalline oxide semiconductor film after forming the second oxide semiconductor film;

forming a gate insulating film over an oxide semiconductor film that comprises the first crystalline oxide semiconductor film and the second crystalline oxide semiconductor film;

forming a first electrode over the gate insulating film;

forming a first sidewall insulating film and a second sidewall insulating film on side surfaces of the first electrode; and

adding a dopant to the oxide semiconductor film to form a first region, a pair of second regions and a pair of third regions of the oxide semiconductor film,

wherein the first electrode overlaps with the first region,

wherein the first sidewall insulating film overlaps with one of the pair of second regions, and the second sidewall insulating film overlaps with the other of the pair of second regions,

wherein the first region and the pair of second regions are located between the pair of third regions,

wherein the first region is a c-axis aligned crystalline oxide semiconductor region,

wherein each of a crystallinity of the pair of second regions and a crystallinity of the pair of third regions is lower than a crystallinity of the first region, and

wherein a dopant concentration of the pair of third regions is higher than a dopant concentration of the pair of second regions.

14. The method for manufacturing a semiconductor device according to claim 13,

wherein the insulating film is formed by a sputtering method.

15. The method for manufacturing a semiconductor device according to claim 14,

wherein the insulating film is formed using a silicon target, a quartz target, an aluminum target, and an aluminum oxide target.

16. The method for manufacturing a semiconductor device according to claim 13,

wherein the proportion of oxygen in the atmosphere gas is 6 vol. % or higher.