Integrated circuit device and structure

• US 9,099,526 B2
• Filed: 10/02/2011
• Issued: 08/04/2015
• Est. Priority Date: 02/16/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): ARORA, AJAY
• Application Number:
  US13/251,269
• Publication Number:
  US 20120091587A1
• Time in Patent Office: 1,402 Days
• Field of Search: 257/357, 257/686
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80009 Pre-treatment of the bonding area
• CPC Class Codes: H01L 2224/80047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/802 Applying energy for connecting
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 : combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A device, including: an integrated circuit chip, where the integrated circuit chip includes: a first layer including a plurality of first transistors including a mono-crystal channel; at least one metal layer overlying the first layer, the at least one metal layer including aluminum or copper and providing interconnection between the first transistors; a second layer overlying the at least one metal layer, the second layer including second horizontally oriented transistors including a second mono-crystal channel; and a through the second layer via of diameter less than 150 nm, where the second horizontally oriented transistors are interconnected to form logic circuits.

Claims

1. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors comprising a mono-crystal channel;

at least one metal layer overlying said first layer, said at least one metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer overlying said at least one metal layer, said second layer comprising second horizontally oriented transistors comprising a second mono-crystal channel; and

a through said second layer via of diameter less than 150 nm,

wherein said second horizontally oriented transistors are interconnected to form logic circuits.

2. The device according to claim 1, further comprising:

thermal conducting paths extending from at least one of said second horizontally oriented transistors to a top or bottom surface of said device,

wherein said thermally conducting paths have a thermal conductivity greater than ten times the thermal conductivity of silicon dioxide.

3. The device according to claim 1,

wherein said second horizontally oriented transistors comprise substantially activated dopant mono-crystal regions.

4. The device according to claim 1,

wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and

wherein said first metal layer has current a carrying capacity substantially higher than said second metal layer.

5. The device according to claim 1,

wherein at least one of said second horizontally oriented transistors comprises a high-K-Metal gate (HKMG).

6. The device according to claim 1, further comprising:

a first alignment mark and a second alignment mark,

wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark;

a connection path between said first transistors and said second transistors comprising said via,

wherein said via is aligned to said first alignment mark and said second alignment mark.

7. The device according to claim 1,

wherein at least one of said second horizontally oriented transistors is lithographically defined with an alignment to said first transistors, and

wherein said alignment comprises an alignment error of less than 40 nm.

8. The device according to claim 1,

wherein said via is lithographically defined with an alignment to said first transistors, and

wherein said alignment comprises an alignment error of less than 40 nm.

9. The device according to claim 1,

wherein at least one of said second horizontally oriented transistors has a back-bias structure.

10. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors comprising a mono-crystal channel;

at least one metal layer overlying said first layer, said at least one metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer overlying said at least one metal layer, said second layer comprising second horizontally oriented transistors comprising a second mono-crystal channel; and

a through said second layer via of diameter less than 150 nm,

wherein at least two of said second horizontally oriented transistors share a common diffusion.

11. The device according to claim 10, further comprising:

thermal conducting paths extending from at least one of said second horizontally oriented transistors to a top or bottom surface of said device,

wherein said thermally conducting paths have a thermal conductivity of greater than ten times the thermal conductivity of silicon dioxide.

12. The device according to claim 10,

wherein said second horizontally oriented transistors comprise substantially activated dopant mono-crystal regions.

13. The device according to claim 10, further comprising:

a first alignment mark and a second alignment mark,

wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark;

a connection path between said first transistors and said second transistors comprising said via,

wherein said via is aligned to said first alignment mark and said second alignment mark.

14. The device according to claim 10,

wherein at least one of said second horizontally oriented transistors comprises a high-K-Metal gate (HKMG).

15. The device according to claim 10,

wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and

wherein said first metal layer has current a carrying capacity substantially higher than said second metal layer.

16. The device according to claim 10,

wherein at least one of said second horizontally oriented transistors is lithographically defined with an alignment to said first transistors,

wherein said alignment comprises an alignment error of less than 40 nm.

17. The device according to claim 10,

wherein said via is lithographically defined with an alignment to said first transistors, and

wherein said alignment comprises an alignment error of less than 40 nm.

18. The device according to claim 10,

wherein at least one of said second horizontally oriented transistors has a back-bias structure.

19. The device according to claim 10,

wherein said second horizontally oriented transistors are interconnected to form an output circuit connecting said device to external devices.

20. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors comprising a mono-crystal channel;

at least one metal layer overlying said first layer, said at least one metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer overlying said at least one metal layer, said second layer comprising a plurality of second horizontally oriented transistors comprising a second mono-crystal channel; and

a through said second layer via of diameter less than 150 nm,

wherein said second horizontally oriented transistors are FinFet transistors.

21. The device according to claim 20, further comprising:

thermal conducting paths extending from at least one of said second horizontally oriented transistors to a top or bottom surface of said device,

wherein said thermally conducting paths have a thermal conductivity of greater than ten times the thermal conductivity of silicon dioxide.

22. The device according to claim 20,

wherein said second horizontally oriented transistors comprise substantially activated dopant mono-crystal regions.

23. The device according to claim 20,

wherein said second horizontally oriented transistors are fully depleted transistors.

24. The device according to claim 20,

wherein at least one of said second horizontally oriented transistors comprises a high-K-Metal gate (HKMG).

25. The device according to claim 20,

wherein at least one of said plurality of second horizontally oriented transistors is lithographically defined with an alignment to said first transistors,

wherein said alignment comprises an alignment error of less than 40 nm.

26. The device according to claim 20,

wherein said via is lithographically defined with an alignment to said first transistors, and

wherein said alignment comprises an alignment error of less than 40 nm.

27. The device according to claim 20,

wherein at least one of said second horizontally oriented transistors has a back-bias structure.

28. The device according to claim 20, further comprising:

a first alignment mark and a second alignment mark,

wherein said first layer comprises said first alignment mark and said second layer comprises said second alignment mark;

a plurality of connection paths between said first transistors and said second transistors comprising said via,

wherein said via is aligned to said first alignment mark and said second alignment mark.

29. The device according to claim 20,

wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and

wherein said first metal layer has current a carrying capacity substantially higher than said second metal layer.

30. The device according to claim 20,

wherein said second horizontally oriented transistors are interconnected to form a plurality of Flip-Flops.