Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods

• US 9,099,539 B2
• Filed: 03/01/2011
• Issued: 08/04/2015
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tuttle, Mark E.
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Kalam, Abul
• Application Number:
  US13/037,785
• Publication Number:
  US 20110151621A1
• Time in Patent Office: 1,617 Days
• Field of Search: 438/668
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.

Claims

1. A method of processing a semiconductor substrate, the semiconductor substrate having integrated circuitry and a plurality of terminals electrically coupled to the integrated circuitry, the method comprising:

forming a plurality of electrically conductive interconnects extending at least partially through the substrate and in contact with corresponding terminals, the interconnects having back side portions at a back side of the semiconductor substrate;

constructing a conductive backplane at the back side of the semiconductor substrate, wherein constructing a conductive backplane at the back side of the semiconductor substrate comprises depositing a conductive layer onto the back side of the substrate, the conductive layer having openings around the interconnects and dielectric spacers in the openings between the conductive layer and the interconnects; and

electrically coupling at least one of the back side portions of the interconnects to the backplane via a conductive coupler in one of the openings and in direct contact with the corresponding interconnect and the conductive layer, and electrically isolating at least one of the plurality of other interconnects from the backplane.

2. The method of claim 1 wherein electrically isolating at least one of the plurality of other interconnects comprises placing another conductive coupler in contact with the back side portion of the other particular interconnect and electrically isolated from the backplane.

3. The method of claim 1 wherein electrically coupling at least one of the back side portions of the interconnects to the backplane comprises electrically coupling at least one of the back side portions of the interconnects to the backplane within the footprint of the semiconductor substrate.

4. The method of claim 1 wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises (a) depositing a metal layer onto the back side of the substrate and electrically isolated from the interconnects, (b) depositing a dielectric layer over the metal layer, and (c) forming the openings in the dielectric layer to at least partially expose the back side portions of the individual interconnects; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises placing a solder ball in a particular opening sized to expose the corresponding interconnect and an adjacent portion of the metal layer, the solder ball being in direct contact with the respective interconnect and the metal layer.

5. The method of claim 1 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect, and wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises—

depositing a first dielectric layer onto the back side of the substrate and in contact with the first and second interconnects;

depositing the conductive layer over the first dielectric layer;

planarizing the substrate by placing the back side of the substrate against a planarizing medium and moving the substrate and/or the planarizing medium relative to each other in a manner that removes portions of the first dielectric layer and conductive layer from the substrate to leave the remaining portions of the conductive layer out of direct contact with the first and second interconnects;

depositing a second dielectric layer over the first dielectric layer and the conductive layer; and

creating a first opening in the second dielectric layer to expose the first interconnect and a portion of the conductive layer, and creating a second opening the second dielectric layer to expose the second interconnect without exposing the conductive layer; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises—

depositing a first conductive coupler into the first opening and in contact with the first interconnect and the conductive layer; and

depositing a second conductive coupler into the second opening and in contact with the second interconnect, wherein the second conductive coupler is out of contact with the conductive layer.

6. The method of claim 5 wherein:

depositing a first dielectric layer comprises depositing a low temperature CVD oxide;

depositing the conductive layer over the first dielectric layer comprises depositing Al, Cu, Ni, W, and/or a conductive polymer; and

depositing a second dielectric layer over the first dielectric layer and the conductive layer comprises depositing a low temperature CVD oxide and/or a photosensitive polyimide.

7. The method of claim 5 wherein the second dielectric layer comprises a low temperature CVD oxide, and wherein creating the first opening and the second opening in the second dielectric layer comprises etching the first and second openings in the second dielectric layer.

8. The method of claim 5 wherein the second dielectric layer comprises a photosensitive polyimide, and wherein creating the first opening and the second opening in the second dielectric layer comprises developing the photosensitive second dielectric layer to have the first and second openings aligned with the first and second interconnects, respectively.

9. A method of processing a semiconductor substrate having a plurality of microelectronic dies, the individual dies including an integrated circuit and bond-pads electrically coupled to the integrated circuit, the method comprising:

constructing a plurality of electrically conductive through-substrate interconnects extending at least partially through the semiconductor substrate and in contact with corresponding bond-pads, wherein the plurality of electrically conductive interconnects comprises first interconnects and second interconnects;

forming a metal layer at a back side of the semiconductor substrate; and

selectively coupling back side portions of the first interconnects of individual dies to the metal layer while keeping the second interconnects of individual dies electrically isolated from the metal layer,

wherein selectively coupling the back side portions of the first interconnects to the metal layer comprises placing solder balls in contact with the back side portions of the first interconnects and portions of the metal layer adjacent to the first interconnects.

10. The method of claim 9 wherein selectively coupling back side portions of the first interconnects of individual dies to the metal layer comprises coupling the back side portions of the first interconnects to the metal layer within the footprint of the respective dies.

11. The method of claim 9, further comprising:

depositing a dielectric layer onto the back side of the substrate and over the metal layer; and

forming first openings in the dielectric layer to expose the back side portions of the first interconnects and adjacent portions of the metal layer, and forming second openings in the dielectric layer to expose a back side portion of the individual second interconnects, wherein the metal layer is isolated from the second openings, and

selectively coupling a back side portion of first interconnects of individual dies to the metal layer while keeping second interconnects of individual dies electrically isolated from the metal layer comprises (a) placing the solder balls in the first openings in direct contact with the corresponding first interconnects and adjacent portions of the metal layer, and (b) placing the solder balls in the second openings in contact with the corresponding second interconnects and electrically isolated from the metal layer.