Three-dimensional system-in-package architecture

• US 9,099,540 B2
• Filed: 04/16/2013
• Issued: 08/04/2015
• Est. Priority Date: 03/06/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Law, Oscar M. K., Wu, Kuo H.
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US13/864,112
• Publication Number:
  US 20130230985A1
• Time in Patent Office: 840 Days
• Field of Search: 438455-459, 438637-640, 438667-668, 438672-675, 438700-701
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a first substrate;

forming one or more first dielectric layers and one or more first metallization layers over the first substrate;

forming a first conductive via through the first substrate and the one or more first dielectric layers and in contact with at least one of the one or more first metallization layers;

forming a plurality of second dielectric layers over the one or more first dielectric layer and the first conductive via; and

forming a second conductive via through the first substrate, the one or more first dielectric layers, and the plurality of second dielectric layers such that the second conductive via has a first end terminating at a first side of the semiconductor device and a second end terminating at a second side of the semiconductor device.

2. The method of claim 1, further comprising:

forming an active device on the first substrate, the at least one of the one or more first metallization layers electrically connecting the active device to the first conductive via.

3. The method of claim 2, further comprising forming a conductive layer on an opposite side of the substrate from the one or more first dielectric layers, the conductive layer in electrical contact with the first conductive via.

4. The method of claim 1, further comprising forming a plurality of conductive interconnects over the first conductive via within the plurality of second dielectric layers.

5. The method of claim 1, wherein the forming the first conductive via further comprises:

forming an opening into a first side of the substrate;

filling the opening with a conductive material; and

thinning a second side of the substrate opposite the first side to expose the conductive material.

6. The method of claim 1, further comprising connecting a third conductive via to the second conductive via, the third conductive via extending through a second substrate.

7. The method of claim 6, further comprising forming metallization layers over the second substrate to electrically connect the third conductive via to an active device located on the second substrate.

8. A method of manufacturing a semiconductor die, the method comprising:

forming a first plurality of dielectric layers over a first side of a semiconductor substrate;

forming a second plurality of dielectric layers over the first plurality of dielectric layers;

forming a first through substrate via to extend through the semiconductor substrate and at least one of the first plurality of dielectric layers, the first through substrate via terminating at a first conductive material located within the first plurality of dielectric layers; and

forming a second through substrate via to extend through the semiconductor substrate, the first plurality of dielectric layers, and the second plurality of dielectric layers, wherein the second through substrate via has a first surface that is planar with a second surface of the first substrate via.

9. The method of claim 8, further comprising:

forming an active device on the semiconductor substrate, the first conductive material electrically connecting the active device to the first conductive via.

10. The method of claim 9, further comprising forming a conductive layer on an opposite side of the semiconductor substrate from the one or more first dielectric layer, the conductive layer in electrical contact with the first conductive via.

11. The method of claim 8, further comprising forming a plurality of conductive interconnects over the first through substrate via within the second plurality of dielectric layers.

12. The method of claim 8, wherein the forming the first conductive via further comprises:

forming an opening into a first side of the semiconductor substrate;

filling the opening with a second conductive material; and

thinning a second side of the semiconductor substrate opposite the first side to expose the second conductive material.

13. The method of claim 8, further comprising connecting a third conductive via to the second through substrate via, the third conductive via extending through a second semiconductor substrate.

14. The method of claim 13, further comprising forming metallization layers over the second semiconductor substrate to electrically connect the third conductive via to an active device located on the second semiconductor substrate.

15. A method of manufacturing a semiconductor device, the method comprising:

forming at least one metallization layer over an interlayer dielectric over a substrate, the substrate comprising a semiconductor material;

forming a first conductive via through the substrate and the interlayer dielectric, at least one metallization layer, the conductive via ending at the at least one metallization layer;

depositing one or more dielectric layers over the at least one metallization layer; and

forming a second conductive via through the substrate and the one or more dielectric layers to have ends on multiple sides of the semiconductor device.

16. The method of claim 15, further comprising:

forming an active device on the substrate, wherein the at least one first metallization layer electrically connecting the active device to the first conductive via.

17. The method of claim 16, further comprising forming a conductive layer on an opposite side of the substrate from the at least one metallization layer, the conductive layer in electrical contact with the first conductive via.

18. The method of claim 15, further comprising forming a plurality of conductive interconnects over the first conductive via.

19. The method of claim 15, wherein the forming the first conductive via further comprises:

forming an opening into a first side of the substrate;

filling the opening with a conductive material; and

thinning a second side of the substrate opposite the first side to expose the conductive material.

20. The method of claim 15, further comprising connecting a third conductive via to the second conductive via, the third conductive via extending through a second substrate.