Multi-core dies produced by reticle set modification

• US 9,099,549 B2
• Filed: 12/02/2013
• Issued: 08/04/2015
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Gaskins, Darius D.
• Primary Examiner(s): Diallo, Mamadou
• Application Number:
  US14/094,206
• Publication Number:
  US 20140084427A1
• Time in Patent Office: 610 Days
• Field of Search: 257/620
• US Class Current: 1/1
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

Claims

1. Multi-core dies produced by a process comprising:

developing a first reticle set usable to print Q-core dies, wherein the first reticle set defines scribe lines to separate the Q-core dies, wherein the scribe lines collectively define a seal ring to surround each Q-core die, wherein Q is at least 1; and

modifying less than all of the reticles of the first reticle set to produce a second reticle set useable to print P-core dies, wherein said modifying comprises removing at least one defined scribe line of the first reticle set and defining inter-core communication wires to connect at least two adjacent cores that were previously separated by the at least one defined scribe line, wherein P is at least twice Q;

printing the multi-core dies on a semiconductor wafer using the second reticle set; and

cutting the multi-core dies on the semiconductor wafer along the remaining scribe lines.

2. The multi-core dies of claim 1, wherein:

the wires enable the at least two connected cores to communicate with each other during operation; and

the wires are not connected to physical input/output landing pads of the P-core dies such that each P-core die does not carry signals through the inter-core communication wires off each P-core die.

3. The multi-core dies of claim 1, wherein Q is 1 and P is 2.

4. The multi-core dies of claim 1, wherein Q is 2 and P is 4.

5. The multi-core dies of claim 1, wherein at least a portion of the wires are employed to enable the at least two connected cores of each multi-core die to communicate with one another for performing power management of each multi-core die.

6. The multi-core dies of claim 5, wherein said performing power management of each multi-core die comprises synchronizing power state changes by the cores.

7. The multi-core dies of claim 5, wherein said performing power management of each multi-core die comprises management of a shared voltage source.

8. The multi-core dies of claim 5, wherein said performing power management of each multi-core die comprises management of a shared clock source.

9. The multi-core dies of claim 1, wherein at least a portion of the wires are employed as an internal bypass bus for bypassing an external bus for interconnecting each multi-core die to a chipset and that supports a multi-processor protocol.

10. The multi-core dies of claim 9, wherein the cores are defined to be configured so that when one of the at least two connected cores drives the external bus, the other cores listen via the internal bypass bus rather than via the external bus.

11. The multi-core dies of claim 1, wherein the first reticle set is usable to print an M×

N matrix of Q-core dies, and wherein the second reticle set is usable to print (N×

M)/2 P-core dies, when M is an even number at least 2 and N is at least 1.

12. The multi-core dies of claim 1, wherein the first reticle set is usable to print an M×

N matrix of Q-core dies, and wherein the modified second reticle set is useable to print both P-core dies and Q-core dies.

13. The multi-core dies of claim 12, wherein the second reticle set is usable to print N×

[(M−

1)/2] P-core dies and M Q-core dies, when M is an odd number at least 3 and N is at least 2.

14. The multi-core dies of claim 12, wherein the second reticle set is usable to print (N×

M)/4 P-core dies and (N×

M)/2 Q-core dies, when M is an even number at least 4 and N is at least 2.

15. The multi-core dies of claim 1, wherein said modifying less than all of the reticles of the first reticle set to produce the second reticle set comprises modifying only corresponding reticles for non-transistor layers of the first reticle set.

16. The multi-core dies of claim 1, wherein said modifying less than all of the reticles of the first reticle set to produce the second reticle set comprises modifying corresponding reticles for fewer than half of all layers of the first reticle set.